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yosys/techlibs
2020-06-30 15:32:06 +02:00
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achronix
anlogic
common simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
coolrunner2
easic
ecp5
efinix
gowin
greenpak4
ice40
intel
intel_alm
sf2
xilinx
.gitignore