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yosys/docs/source/yosys_internals
Gary Wong 5feb1a1752 verilog: add support for SystemVerilog string literals.
Differences are new escape sequences (including escaped newline
continuations and hex escapes) and triple-quoted literals.
2025-07-03 20:51:12 -06:00
..
extending_yosys
flow
formats
hashing.rst
index.rst
techmap.rst
verilog.rst