Clifford Wolf 0e0c80fac8 Add support for zero-width signals to Verilog back-end, fixes #948 ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2019-04-22 19:44:42 +02:00
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verilog	Add support for zero-width signals to Verilog back-end, fixes #948	2019-04-22 19:44:42 +02:00