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e34a25ea27
Blocking tasks are now capital TODO (compared to non-blocking todo). Updated some of the todos. Added note about which intel synth does which families. Rename extended Yosys universe to Yosys family. Added brief text to landing page, and also a note about the restructure and where to find old docs. Moved todolist above ToC in preparation for disabling it in the config (so that it doesn't need it's own header). Fixed pdf build, was previously breaking on trying to include the svg badges.
40 lines
1.3 KiB
ReStructuredText
40 lines
1.3 KiB
ReStructuredText
The :cmd:ref:`abc` command
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~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. TODO:: discuss abc, consider using https://github.com/Ravenslofty/yosys-cookbook/blob/master/misc/abc9.md
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The :cmd:ref:`abc` command provides an interface to ABC_, an open source tool
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for low-level logic synthesis.
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.. _ABC: http://www.eecs.berkeley.edu/~alanmi/abc/
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The :cmd:ref:`abc` command processes a netlist of internal gate types and can
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perform:
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- logic minimization (optimization)
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- mapping of logic to standard cell library (liberty format)
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- mapping of logic to k-LUTs (for FPGA synthesis)
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Optionally :cmd:ref:`abc` can process registers from one clock domain and
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perform sequential optimization (such as register balancing).
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ABC is also controlled using scripts. An ABC script can be specified to use more
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advanced ABC features. It is also possible to write the design with
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:cmd:ref:`write_blif` and load the output file into ABC outside of Yosys.
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Example
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^^^^^^^
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.. todo:: describe ``abc`` images
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.. literalinclude:: /code_examples/synth_flow/abc_01.v
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:language: verilog
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:caption: ``docs/source/code_examples/synth_flow/abc_01.v``
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.. literalinclude:: /code_examples/synth_flow/abc_01.ys
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:language: yoscrypt
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:caption: ``docs/source/code_examples/synth_flow/abc_01.ys``
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.. figure:: /_images/code_examples/synth_flow/abc_01.*
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:class: width-helper
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