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e34a25ea27
Blocking tasks are now capital TODO (compared to non-blocking todo). Updated some of the todos. Added note about which intel synth does which families. Rename extended Yosys universe to Yosys family. Added brief text to landing page, and also a note about the restructure and where to find old docs. Moved todolist above ToC in preparation for disabling it in the config (so that it doesn't need it's own header). Fixed pdf build, was previously breaking on trying to include the svg badges.
166 lines
5.8 KiB
ReStructuredText
166 lines
5.8 KiB
ReStructuredText
Scripting in Yosys
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------------------
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.. TODO:: logical consistency, esp with example_synth
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Yosys reads and processes commands from synthesis scripts, command line
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arguments and an interactive command prompt. Yosys commands consist of a command
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name and an optional whitespace separated list of arguments. Commands are
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terminated using the newline character or a semicolon (;). Empty lines and lines
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starting with the hash sign (#) are ignored. Also see :doc:`example_synth`.
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The command :cmd:ref:`help` can be used to access the command reference manual,
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with ``help <command>`` providing details for a specific command. ``yosys -H``
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or ``yosys -h <command>`` will do the same outside of an interactive prompt.
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The entire reference manual is also available here at :doc:`/cmd_ref`.
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Example commands
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~~~~~~~~~~~~~~~~
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Commands for design navigation and investigation:
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.. code-block:: yoscrypt
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cd # a shortcut for 'select -module <name>'
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ls # list modules or objects in modules
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dump # print parts of the design in RTLIL format
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show # generate schematics using graphviz
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select # modify and view the list of selected objects
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Commands for executing scripts or entering interactive mode:
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.. code-block:: yoscrypt
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shell # enter interactive command mode
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history # show last interactive commands
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script # execute commands from script file
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tcl # execute a TCL script file
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Commands for reading and elaborating the design:
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.. code-block:: yoscrypt
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read_rtlil # read modules from RTLIL file
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read_verilog # read modules from Verilog file
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hierarchy # check, expand and clean up design hierarchy
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Commands for high-level synthesis:
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.. code-block:: yoscrypt
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proc # translate processes to netlists
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fsm # extract and optimize finite state machines
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memory # translate memories to basic cells
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opt # perform simple optimizations
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Commands for technology mapping:
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.. code-block:: yoscrypt
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techmap # generic technology mapper
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abc # use ABC for technology mapping
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dfflibmap # technology mapping of flip-flops
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hilomap # technology mapping of constant hi- and/or lo-drivers
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iopadmap # technology mapping of i/o pads (or buffers)
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flatten # flatten design
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Commands for writing the results:
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.. code-block:: yoscrypt
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write_blif # write design to BLIF file
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write_btor # write design to BTOR file
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write_edif # write design to EDIF netlist file
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write_rtlil # write design to RTLIL file
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write_spice # write design to SPICE netlist file
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write_verilog # write design to Verilog file
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Script-Commands for standard synthesis tasks:
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.. code-block:: yoscrypt
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synth # generic synthesis script
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synth_xilinx # synthesis for Xilinx FPGAs
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Commands for model checking:
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.. code-block:: yoscrypt
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sat # solve a SAT problem in the circuit
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miter # automatically create a miter circuit
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scc # detect strongly connected components (logic loops)
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Selections intro
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~~~~~~~~~~~~~~~~
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.. todo:: reorder text for logical consistency
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Most commands can operate not only on the entire design but also specifically on
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selected parts of the design. For example the command :cmd:ref:`dump` will print
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all selected objects in the current design while ``dump foobar`` will only print
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the module ``foobar`` and ``dump *`` will print the entire design regardless of
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the current selection.
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.. code:: yoscrypt
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dump */t:$add %x:+[A] */w:* %i
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The selection mechanism is very powerful. For example the command above will
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print all wires that are connected to the ``\A`` port of a ``$add`` cell.
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Detailed documentation of the select framework can be found under
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:doc:`/using_yosys/more_scripting/selections` or in the command reference at
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:doc:`/cmd/select`.
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The show command
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~~~~~~~~~~~~~~~~
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The :cmd:ref:`show` command requires a working installation of `GraphViz`_ and
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`xdot`_ for generating the actual circuit diagrams. Below is an example of how
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this command can be used, showing the changes in the generated circuit at
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different stages of the yosys tool flow.
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.. _GraphViz: http://www.graphviz.org/
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.. _xdot: https://github.com/jrfonseca/xdot.py
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.. literalinclude:: /code_examples/show/example.ys
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:language: yoscrypt
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:caption: docs/source/code_examples/show/example.ys
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.. literalinclude:: /code_examples/show/example.v
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:language: Verilog
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:caption: docs/source/code_examples/show/example.v
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.. role:: yoscrypt(code)
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:language: yoscrypt
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.. figure:: /_images/code_examples/show/example_00.*
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:class: width-helper
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``example_00`` - shown after :yoscrypt:`read_verilog example.v`
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.. figure:: /_images/code_examples/show/example_01.*
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:class: width-helper
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``example_01`` - shown after :yoscrypt:`proc`
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.. figure:: /_images/code_examples/show/example_02.*
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:class: width-helper
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``example_02`` - shown after :yoscrypt:`opt`
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A circuit diagram is generated for the design in its current state. Various
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options can be used to change the appearance of the circuit diagram, set the
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name and format for the output file, and so forth. When called without any
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special options, it saves the circuit diagram in a temporary file and launches
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``xdot`` to display the diagram. Subsequent calls to show re-use the ``xdot``
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instance (if still running).
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For more information on the :cmd:ref:`show` command, including a guide on what
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the different symbols represent, see :ref:`interactive_show` and the
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:doc:`/using_yosys/more_scripting/interactive_investigation` page.
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