mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 19:52:31 +00:00 
			
		
		
		
	- Simplify synthetic localparams for normal calls to update their width
    - This step was inadvertently removed alongside `added_mod_children`
- Support redeclaration of constant function arguments
    - `eval_const_function` never correctly handled this, but the issue
      was not exposed in the existing tests until the recent change to
      always attempt constant function evaluation when all-const args
      are used
- Check asserts in const_arg_loop and const_func tests
- Add coverage for width mismatch error cases
		
	
			
		
			
				
	
	
		
			12 lines
		
	
	
	
		
			263 B
		
	
	
	
		
			Text
		
	
	
	
	
	
			
		
		
	
	
			12 lines
		
	
	
	
		
			263 B
		
	
	
	
		
			Text
		
	
	
	
	
	
| logger -expect error "Incompatible re-declaration of wire" 1
 | |
| read_verilog -sv <<EOT
 | |
| module top;
 | |
|     function automatic integer f;
 | |
|         input [0:0] inp;
 | |
|         integer inp;
 | |
|         f = inp;
 | |
|     endfunction
 | |
|     integer x, y;
 | |
|     initial x = f(y);
 | |
| endmodule
 | |
| EOT
 |