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Code Activity
yosys/tests/arch/ecp5
History
Mohamed Gaber 58e831486d
pyosys: __getitem__ for supported classes 
- functions that have a const `[]` operator method now support `__getitem__` in Python
- fields of a pointer type now return a `reference_internal` instead of a `copy` because classes referenced to by pointers typically aren't copyable (e.g. RTLIL::Wire, RTLIL::Module, etc)
- removed duplicate of test_script.py
2025-11-19 18:09:41 +02:00
..
add_sub.ys ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
adffs.ys Share common tests 2019-10-18 12:19:59 +02:00
bug1459.ys Add testcase from #1459 2020-01-06 16:22:22 -08:00
bug1598.ys Add #1598 testcase 2019-12-27 16:44:57 -08:00
bug1630.il.gz Add #1630 testcase 2020-01-13 21:27:53 -08:00
bug1630.ys Remove references to ilang 2024-11-05 12:36:31 +13:00
bug1836.mem Addings tests for #1836 and #3205 2023-02-21 05:23:14 +13:00
bug1836.ys Genericising bug1836.ys 2023-02-21 05:23:16 +13:00
bug2409.ys memory_dff: Fix needlessly duplicating enable bits. 2020-10-22 13:03:42 +02:00
bug2731.ys abc9: replace cell type/parameters if derived type already processed (#2991) 2021-09-09 10:05:55 -07:00
counter.ys ice40, ecp5, gowin: enable ABC9 by default 2023-11-13 15:28:13 +00:00
dffs.ys Share common tests 2019-10-18 12:19:59 +02:00
dpram.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
dpram.ys Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
fsm.ys Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
latches.ys Share common tests 2019-10-18 12:19:59 +02:00
latches_abc9.ys tests: tidy up testcase 2020-06-03 08:41:55 -07:00
logic.ys Share common tests 2019-10-18 12:19:59 +02:00
lutram.ys memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
macc.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
macc.ys Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
memories.ys Testing TDP synth mapping 2023-02-21 05:23:15 +13:00
mul.ys Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
mux.ys Update tests 2023-06-09 14:41:45 +02:00
opt_lut_ins.ys Remove references to ilang 2024-11-05 12:36:31 +13:00
rom.v Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
rom.ys Moved all tests in arch sub directory 2019-10-18 11:06:12 +02:00
run-test.sh test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
shifter.ys Share common tests 2019-10-18 12:19:59 +02:00
tribuf.ys Share common tests 2019-10-18 12:19:59 +02:00