Jim Lawson 171c425cf9 Fix FIRRTL to Verilog process instance subfield assignment. ... Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)		2019-02-25 16:18:13 -08:00
..
.gitignore	added more .gitignore files (make test)	2013-01-05 11:35:52 +01:00
autotest.mk	Update cells supported for verilog to FIRRTL conversion.	2019-02-15 11:14:17 -08:00
autotest.sh	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
cmp_tbdata.c	Fix for modules with big interfaces.	2016-09-13 13:13:27 +03:00
profiler.pl	initial import	2013-01-05 11:13:26 +01:00
txt2tikztiming.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
vcd2txt.pl	Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)	2014-02-19 12:40:49 +01:00
vcdcd.pl	Spell check (by Larry Doolittle)	2015-08-14 10:56:05 +02:00