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e2e7065590
- Filling out index descriptions for `using_yosys` and `using_yosys/synthesis`. - To discourage skipping over these index pages, the toctree in `using_yosys/index` is hidden and instead has inline links to the two subsections. - Tidying todos. - Moves technology mapping to `techmap_synth`, leaving the techmap by example in the internals section. `yosys_flows` gets split up, with the coarse-grain intro replaced by `synthesis/index`, the extract pass moving to `synthesis/extract` and model checking to `more_scripting/model_checking`.
36 lines
1.3 KiB
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36 lines
1.3 KiB
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Synthesis in detail
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-------------------
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Synthesis can generally be broken down into coarse-grain synthesis, and
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fine-grain synthesis. We saw this in :doc:`/getting_started/example_synth`
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where a design was loaded and elaborated and then went through a series of
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coarse-grain optimizations before being mapped to hard blocks and fine-grain
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cells. Most commands in Yosys will target either coarse-grain representation or
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fine-grain representation, with only a select few compatible with both states.
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Commands such as :cmd:ref:`proc`, :cmd:ref:`fsm`, and :cmd:ref:`memory` rely on
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the additional information in the coarse-grain representation, along with a
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number of optimizations such as :cmd:ref:`wreduce`, :cmd:ref:`share`, and
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:cmd:ref:`alumacc`. :cmd:ref:`opt` provides optimizations which are useful in
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both states, while :cmd:ref:`techmap` is used to convert coarse-grain cells
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to the corresponding fine-grain representation.
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Single-bit cells (logic gates, FFs) as well as LUTs, half-adders, and
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full-adders make up the bulk of the fine-grain representation and are necessary
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for commands such as :cmd:ref:`abc`\ /:cmd:ref:`abc9`, :cmd:ref:`simplemap`,
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:cmd:ref:`dfflegalize`, and :cmd:ref:`memory_map`.
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.. toctree::
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:maxdepth: 3
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synth
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proc
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fsm
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memory
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opt
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techmap_synth
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extract
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abc
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cell_libs
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