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20c2708383
Rework images makefile a bit to get it to import and build from resources folder(s). Currently requires running twice from a clean build due to the way it finds `.dot` files to convert.
12 lines
190 B
Verilog
12 lines
190 B
Verilog
module counter (clk, rst, en, count);
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input clk, rst, en;
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output reg [1:0] count;
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always @(posedge clk)
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if (rst)
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count <= 2'd0;
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else if (en)
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count <= count + 2'd1;
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endmodule
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