mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-28 11:25:53 +00:00
3 lines
78 B
Verilog
3 lines
78 B
Verilog
module test(input A, B, output Y);
|
|
assign Y = A ? A ? B : 1'b1 : B;
|
|
endmodule
|