Akash Levy 7a35a982d3 Merge pull request #111 from Silimate/timing_balance_impl ... silimate: add opt_timing_balance pass and tests		2026-02-28 12:22:23 -08:00
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cmds	Merge from main	2026-02-13 04:14:08 -08:00
equiv
fsm
hierarchy
memory	Fix cell naming issues	2026-02-13 01:05:51 -08:00
opt	Improve wreduce runtime	2026-02-19 01:03:26 -08:00
pmgen
proc
sat	Added built in cell alongside sim support for cell	2026-02-19 11:48:35 -08:00
silimate	Merge pull request #111 from Silimate/timing_balance_impl	2026-02-28 12:22:23 -08:00
techmap	Added is_clock_gated attr to flops created via clockgate.cc pass	2026-02-20 11:34:08 -08:00
tests