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https://github.com/YosysHQ/yosys
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189 lines
2.3 KiB
Text
189 lines
2.3 KiB
Text
# Good case: proper feedback port.
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read_verilog << EOT
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module top(...);
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input clk;
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input en;
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input s;
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input [3:0] ra;
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output [15:0] rd;
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input [3:0] wa;
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input [15:0] wd;
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reg [15:0] mem[0:15];
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assign rd = mem[ra];
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always @(posedge clk) begin
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if (en) begin
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mem[wa] <= {mem[wa][15:8], s ? wd[7:0] : mem[wa][7:0]};
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end
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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design -save start
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memory_map
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design -save preopt
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design -load start
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opt_mem_feedback
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select -assert-count 1 t:$memrd_v2
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memory_map
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design -save postopt
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equiv_opt -assert -run prepare: :
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design -reset
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# Bad case: read port also used for other things.
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read_verilog << EOT
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module top(...);
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input clk;
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input en;
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input s;
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output [15:0] rd;
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input [3:0] wa;
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input [15:0] wd;
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reg [15:0] mem[0:15];
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assign rd = mem[wa];
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always @(posedge clk) begin
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if (en) begin
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mem[wa] <= {s ? rd : wd[15:8], s ? wd[7:0] : rd};
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end
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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design -save start
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memory_map
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design -save preopt
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design -load start
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select -assert-count 1 t:$memrd
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opt_mem_feedback
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select -assert-count 1 t:$memrd
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memory_map
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design -save postopt
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equiv_opt -assert -run prepare: :
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design -reset
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# Bad case: another user of the mux out.
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read_verilog << EOT
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module top(...);
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input clk;
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input en;
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input s;
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output [15:0] rd;
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input [3:0] wa;
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input [15:0] wd;
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reg [15:0] mem[0:15];
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assign rd = s ? wd : mem[wa];
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always @(posedge clk) begin
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if (en) begin
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mem[wa] <= rd;
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end
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end
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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design -save start
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memory_map
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design -save preopt
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design -load start
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select -assert-count 1 t:$memrd
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opt_mem_feedback
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select -assert-count 1 t:$memrd
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memory_map
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design -save postopt
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equiv_opt -assert -run prepare: :
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design -reset
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# Tricky case: legit feedback path, but priority needs to be preserved.
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read_verilog << EOT
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module top(...);
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input clk;
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input sel;
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input [3:0] wa1;
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input [3:0] wa2;
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input [15:0] wd1;
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input [3:0] ra;
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output [15:0] rd;
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reg [15:0] mem [0:15];
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always @(posedge clk) begin
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mem[wa1] <= sel ? wd1 : mem[wa1];
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mem[wa2] <= mem[wa2];
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end
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assign rd = mem[ra];
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endmodule
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EOT
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hierarchy -auto-top
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proc
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opt_clean
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design -save start
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memory_map
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design -save preopt
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design -load start
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opt_mem_feedback
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select -assert-count 1 t:$memrd_v2
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memory_map
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design -save postopt
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equiv_opt -assert -run prepare: :
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