mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
38a0c30d65
This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
792 lines
33 KiB
Plaintext
792 lines
33 KiB
Plaintext
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List of major changes and improvements between releases
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=======================================================
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Yosys 0.9 .. Yosys 0.9-dev
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--------------------------
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* Various
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- Added "write_xaiger" backend
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- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
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- Added "synth_xilinx -abc9" (experimental)
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- Added "synth_ice40 -abc9" (experimental)
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- Added "synth -abc9" (experimental)
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- Added "script -scriptwire"
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- Added "synth_xilinx -nocarry"
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- Added "synth_xilinx -nowidelut"
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- Added "synth_ecp5 -nowidelut"
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- "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
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- Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
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- Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
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- Renamed labels in synth_intel (e.g. bram -> map_bram)
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- Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
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- Added automatic gzip decompression for frontends
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- Added $_NMUX_ cell type
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- Added automatic gzip compression (based on filename extension) for backends
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- Improve attribute and parameter encoding in JSON to avoid ambiguities between
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bit vectors and strings containing [01xz]*
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- Added "clkbufmap" pass
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- Added "extractinv" pass and "invertible_pin" attribute
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- Added "synth_xilinx -family xc6s" for Spartan 6 support (experimental)
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- Added "synth_xilinx -ise" (experimental)
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- Added "synth_xilinx -iopad"
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- "synth_xilinx" now automatically inserts clock buffers (add -noclkbuf to disable)
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- Improvements in pmgen: subpattern and recursive matches
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- Added "opt_share" pass, run as part of "opt -full"
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- Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
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- Removed "ice40_unlut"
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- Improvements in pmgen: slices, choices, define, generate
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- Added "xilinx_srl" for Xilinx shift register extraction
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- Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
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- Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
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- Added "-match-init" option to "dff2dffs" pass
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- Added "techmap_autopurge" support to techmap
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- Added "add -mod <modname[s]>"
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- Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
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- Added "ice40_dsp" for Lattice iCE40 DSP packing
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- Added "xilinx_dsp" for Xilinx DSP packing
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- "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
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- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)
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- "synth_ice40 -dsp" to infer DSP blocks
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- Added latch support to synth_xilinx
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- Added support for flip-flops with synchronous reset to synth_xilinx
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- Added support for flip-flops with reset and enable to synth_xilinx
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- Added "check -mapped"
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- Added checking of SystemVerilog always block types (always_comb,
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always_latch and always_ff)
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- Added support for SystemVerilog wildcard port connections (.*)
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- Added "xilinx_dffopt" pass
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- Added "scratchpad" pass
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- Added "abc9 -dff"
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- Added "synth_xilinx -dff"
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- Improved support of $readmem[hb] Memory Content File inclusion
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- Added "opt_lut_ins" pass
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- Added "logger" pass
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- Removed "dffsr2dff" (use opt_rmdff instead)
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Yosys 0.8 .. Yosys 0.9
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----------------------
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* Various
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- Many bugfixes and small improvements
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- Added support for SystemVerilog interfaces and modports
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- Added "write_edif -attrprop"
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- Added "opt_lut" pass
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- Added "gate2lut.v" techmap rule
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- Added "rename -src"
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- Added "equiv_opt" pass
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- Added "flowmap" LUT mapping pass
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- Added "rename -wire" to rename cells based on the wires they drive
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- Added "bugpoint" for creating minimised testcases
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- Added "write_edif -gndvccy"
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- "write_verilog" to escape Verilog keywords
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- Fixed sign handling of real constants
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- "write_verilog" to write initial statement for initial flop state
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- Added pmgen pattern matcher generator
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- Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
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- Added "setundef -params" to replace undefined cell parameters
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- Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
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- Fixed handling of defparam when default_nettype is none
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- Fixed "wreduce" flipflop handling
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- Fixed FIRRTL to Verilog process instance subfield assignment
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- Added "write_verilog -siminit"
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- Several fixes and improvements for mem2reg memories
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- Fixed handling of task output ports in clocked always blocks
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- Improved handling of and-with-1 and or-with-0 in "opt_expr"
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- Added "read_aiger" frontend
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- Added "mutate" pass
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- Added "hdlname" attribute
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- Added "rename -output"
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- Added "read_ilang -lib"
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- Improved "proc" full_case detection and handling
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- Added "whitebox" and "lib_whitebox" attributes
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- Added "read_verilog -nowb", "flatten -wb" and "wbflip"
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- Added Python bindings and support for Python plug-ins
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- Added "pmux2shiftx"
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- Added log_debug framework for reduced default verbosity
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- Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
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- Added "peepopt" peephole optimisation pass using pmgen
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- Added approximate support for SystemVerilog "var" keyword
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- Added parsing of "specify" blocks into $specrule and $specify[23]
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- Added support for attributes on parameters and localparams
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- Added support for parsing attributes on port connections
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- Added "wreduce -keepdc"
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- Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
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- Added Verilog wand/wor wire type support
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- Added support for elaboration system tasks
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- Added "muxcover -mux{4,8,16}=<cost>"
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- Added "muxcover -dmux=<cost>"
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- Added "muxcover -nopartial"
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- Added "muxpack" pass
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- Added "pmux2shiftx -norange"
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- Added support for "~" in filename parsing
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- Added "read_verilog -pwires" feature to turn parameters into wires
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- Fixed sign extension of unsized constants with 'bx and 'bz MSB
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- Fixed genvar to be a signed type
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- Added support for attributes on case rules
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- Added "upto" and "offset" to JSON frontend and backend
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- Several liberty file parser improvements
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- Fixed handling of more complex BRAM patterns
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- Add "write_aiger -I -O -B"
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* Formal Verification
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- Added $changed support to read_verilog
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- Added "read_verilog -noassert -noassume -assert-assumes"
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- Added btor ops for $mul, $div, $mod and $concat
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- Added yosys-smtbmc support for btor witnesses
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- Added "supercover" pass
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- Fixed $global_clock handling vs autowire
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- Added $dffsr support to "async2sync"
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- Added "fmcombine" pass
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- Added memory init support in "write_btor"
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- Added "cutpoint" pass
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- Changed "ne" to "neq" in btor2 output
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- Added support for SVA "final" keyword
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- Added "fmcombine -initeq -anyeq"
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- Added timescale and generated-by header to yosys-smtbmc vcd output
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- Improved BTOR2 handling of undriven wires
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* Verific support
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- Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
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- Improved support for asymmetric memories
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- Added "verific -chparam"
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- Fixed "verific -extnets" for more complex situations
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- Added "read -verific" and "read -noverific"
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- Added "hierarchy -chparam"
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* New back-ends
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- Added initial Anlogic support
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- Added initial SmartFusion2 and IGLOO2 support
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* ECP5 support
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- Added "synth_ecp5 -nowidelut"
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- Added BRAM inference support to "synth_ecp5"
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- Added support for transforming Diamond IO and flipflop primitives
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* iCE40 support
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- Added "ice40_unlut" pass
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- Added "synth_ice40 -relut"
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- Added "synth_ice40 -noabc"
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- Added "synth_ice40 -dffe_min_ce_use"
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- Added DSP inference support using pmgen
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- Added support for initialising BRAM primitives from a file
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- Added iCE40 Ultra RGB LED driver cells
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* Xilinx support
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- Use "write_edif -pvector bra" for Xilinx EDIF files
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- Fixes for VPR place and route support with "synth_xilinx"
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- Added more cell simulation models
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- Added "synth_xilinx -family"
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- Added "stat -tech xilinx" to estimate logic cell usage
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- Added "synth_xilinx -nocarry"
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- Added "synth_xilinx -nowidelut"
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- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
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- Added support for mapping RAM32X1D
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Yosys 0.7 .. Yosys 0.8
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----------------------
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* Various
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- Many bugfixes and small improvements
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- Strip debug symbols from installed binary
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- Replace -ignore_redef with -[no]overwrite in front-ends
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- Added write_verilog hex dump support, add -nohex option
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- Added "write_verilog -decimal"
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- Added "scc -set_attr"
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- Added "verilog_defines" command
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- Remember defines from one read_verilog to next
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- Added support for hierarchical defparam
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- Added FIRRTL back-end
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- Improved ABC default scripts
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- Added "design -reset-vlog"
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- Added "yosys -W regex", "yosys -w regex", and "yosys -e regex"
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- Added Verilog $rtoi and $itor support
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- Added "check -initdrv"
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- Added "read_blif -wideports"
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- Added support for SystemVerilog "++" and "--" operators
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- Added support for SystemVerilog unique, unique0, and priority case
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- Added "write_edif" options for edif "flavors"
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- Added support for resetall compiler directive
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- Added simple C beck-end (bitwise combinatorical only atm)
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- Added $_ANDNOT_ and $_ORNOT_ cell types
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- Added cell library aliases to "abc -g"
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- Added "setundef -anyseq"
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- Added "chtype" command
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- Added "design -import"
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- Added "write_table" command
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- Added "read_json" command
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- Added "sim" command
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- Added "extract_fa" and "extract_reduce" commands
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- Added "extract_counter" command
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- Added "opt_demorgan" command
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- Added support for $size and $bits SystemVerilog functions
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- Added "blackbox" command
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- Added "ltp" command
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- Added support for editline as replacement for readline
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- Added warnings for driver-driver conflicts between FFs (and other cells) and constants
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- Added "yosys -E" for creating Makefile dependencies files
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- Added "synth -noshare"
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- Added "memory_nordff"
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- Added "setundef -undef -expose -anyconst"
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- Added "expose -input"
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- Added specify/specparam parser support (simply ignore them)
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- Added "write_blif -inames -iattr"
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- Added "hierarchy -simcheck"
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- Added an option to statically link abc into yosys
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- Added protobuf back-end
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- Added BLIF parsing support for .conn and .cname
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- Added read_verilog error checking for reg/wire/logic misuse
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- Added "make coverage" and ENABLE_GCOV build option
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* Changes in Yosys APIs
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- Added ConstEval defaultval feature
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- Added {get,set}_src_attribute() methods on RTLIL::AttrObject
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- Added SigSpec::is_fully_ones() and Const::is_fully_ones()
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- Added log_file_warning() and log_file_error() functions
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* Formal Verification
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- Added "write_aiger"
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- Added "yosys-smtbmc --aig"
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- Added "always <positive_int>" to .smtc format
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- Added $cover cell type and support for cover properties
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- Added $fair/$live cell type and support for liveness properties
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- Added smtbmc support for memory vcd dumping
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- Added "chformal" command
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- Added "write_smt2 -stbv" and "write_smt2 -stdt"
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- Fix equiv_simple, old behavior now available with "equiv_simple -short"
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- Change to Yices2 as default SMT solver (it is GPL now)
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- Added "yosys-smtbmc --presat" (now default in SymbiYosys)
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- Added "yosys-smtbmc --smtc-init --smtc-top --noinit"
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- Added a brand new "write_btor" command for BTOR2
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- Added clk2fflogic memory support and other improvements
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- Added "async memory write" support to write_smt2
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- Simulate clock toggling in yosys-smtbmc VCD output
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- Added $allseq/$allconst cells for EA-solving
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- Make -nordff the default in "prep"
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- Added (* gclk *) attribute
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- Added "async2sync" pass for single-clock designs with async resets
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* Verific support
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- Many improvements in Verific front-end
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- Added proper handling of concurent SVA properties
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- Map "const" and "rand const" to $anyseq/$anyconst
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- Added "verific -import -flatten" and "verific -import -extnets"
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- Added "verific -vlog-incdir -vlog-define -vlog-libdir"
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- Remove PSL support (because PSL has been removed in upstream Verific)
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- Improve integration with "hierarchy" command design elaboration
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- Added YOSYS_NOVERIFIC for running non-verific test cases with verific bin
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- Added simpilied "read" command that automatically uses verific if available
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- Added "verific -set-<severity> <msg_id>.."
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- Added "verific -work <libname>"
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* New back-ends
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- Added initial Coolrunner-II support
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- Added initial eASIC support
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- Added initial ECP5 support
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* GreenPAK Support
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- Added support for GP_DLATCH, GP_SPI, GP_DCMx, GP_COUNTx, etc.
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* iCE40 Support
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- Add "synth_ice40 -vpr"
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- Add "synth_ice40 -nodffe"
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- Add "synth_ice40 -json"
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- Add Support for UltraPlus cells
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* MAX10 and Cyclone IV Support
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- Added initial version of metacommand "synth_intel".
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- Improved write_verilog command to produce VQM netlist for Quartus Prime.
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- Added support for MAX10 FPGA family synthesis.
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- Added support for Cyclone IV family synthesis.
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- Added example of implementation for DE2i-150 board.
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- Added example of implementation for MAX10 development kit.
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- Added LFSR example from Asic World.
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- Added "dffinit -highlow" for mapping to Intel primitives
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Yosys 0.6 .. Yosys 0.7
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----------------------
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* Various
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- Added "yosys -D" feature
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- Added support for installed plugins in $(DATDIR)/plugins/
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- Renamed opt_const to opt_expr
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- Renamed opt_share to opt_merge
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- Added "prep -flatten" and "synth -flatten"
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- Added "prep -auto-top" and "synth -auto-top"
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- Using "mfs" and "lutpack" in ABC lut mapping
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- Support for abstract modules in chparam
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- Cleanup abstract modules at end of "hierarchy -top"
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- Added tristate buffer support to iopadmap
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- Added opt_expr support for div/mod by power-of-two
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- Added "select -assert-min <N> -assert-max <N>"
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- Added "attrmvcp" pass
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- Added "attrmap" command
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- Added "tee +INT -INT"
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- Added "zinit" pass
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- Added "setparam -type"
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- Added "shregmap" pass
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- Added "setundef -init"
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- Added "nlutmap -assert"
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- Added $sop cell type and "abc -sop -I <num> -P <num>"
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- Added "dc2" to default ABC scripts
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- Added "deminout"
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- Added "insbuf" command
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- Added "prep -nomem"
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- Added "opt_rmdff -keepdc"
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- Added "prep -nokeepdc"
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- Added initial version of "synth_gowin"
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- Added "fsm_expand -full"
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- Added support for fsm_encoding="user"
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- Many improvements in GreenPAK4 support
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- Added black box modules for all Xilinx 7-series lib cells
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- Added synth_ice40 support for latches via logic loops
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- Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"
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* Build System
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- Added ABCEXTERNAL and ABCURL make variables
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- Added BINDIR, LIBDIR, and DATDIR make variables
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- Added PKG_CONFIG make variable
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- Added SEED make variable (for "make test")
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- Added YOSYS_VER_STR make variable
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- Updated min GCC requirement to GCC 4.8
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- Updated required Bison version to Bison 3.x
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* Internal APIs
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- Added ast.h to exported headers
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- Added ScriptPass helper class for script-like passes
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- Added CellEdgesDatabase API
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* Front-ends and Back-ends
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- Added filename glob support to all front-ends
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- Added avail (black-box) module params to ilang format
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- Added $display %m support
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- Added support for $stop Verilog system task
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- Added support for SystemVerilog packages
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- Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}
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- Added support for "active high" and "active low" latches in read_blif and write_blif
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- Use init value "2" for all uninitialized FFs in BLIF back-end
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- Added "read_blif -sop"
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- Added "write_blif -noalias"
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- Added various write_blif options for VTR support
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- write_json: also write module attributes.
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- Added "write_verilog -nodec -nostr -defparam"
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- Added "read_verilog -norestrict -assume-asserts"
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- Added support for bus interfaces to "read_liberty -lib"
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- Added liberty parser support for types within cell decls
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- Added "write_verilog -renameprefix -v"
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- Added "write_edif -nogndvcc"
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* Formal Verification
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- Support for hierarchical designs in smt2 back-end
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- Yosys-smtbmc: Support for hierarchical VCD dumping
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- Added $initstate cell type and vlog function
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- Added $anyconst and $anyseq cell types and vlog functions
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- Added printing of code loc of failed asserts to yosys-smtbmc
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- Added memory_memx pass, "memory -memx", and "prep -memx"
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- Added "proc_mux -ifx"
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- Added "yosys-smtbmc -g"
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- Deprecated "write_smt2 -regs" (by default on now)
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- Made "write_smt2 -bv -mem" default, added "write_smt2 -nobv -nomem"
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- Added support for memories to smtio.py
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- Added "yosys-smtbmc --dump-vlogtb"
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- Added "yosys-smtbmc --smtc --dump-smtc"
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- Added "yosys-smtbmc --dump-all"
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- Added assertpmux command
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- Added "yosys-smtbmc --unroll"
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- Added $past, $stable, $rose, $fell SVA functions
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- Added "yosys-smtbmc --noinfo and --dummy"
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- Added "yosys-smtbmc --noincr"
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- Added "yosys-smtbmc --cex <filename>"
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- Added $ff and $_FF_ cell types
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- Added $global_clock verilog syntax support for creating $ff cells
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- Added clk2fflogic
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Yosys 0.5 .. Yosys 0.6
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----------------------
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* Various
|
|
- Added Contributor Covenant Code of Conduct
|
|
- Various improvements in dict<> and pool<>
|
|
- Added hashlib::mfp and refactored SigMap
|
|
- Improved support for reals as module parameters
|
|
- Various improvements in SMT2 back-end
|
|
- Added "keep_hierarchy" attribute
|
|
- Verilog front-end: define `BLACKBOX in -lib mode
|
|
- Added API for converting internal cells to AIGs
|
|
- Added ENABLE_LIBYOSYS Makefile option
|
|
- Removed "techmap -share_map" (use "-map +/filename" instead)
|
|
- Switched all Python scripts to Python 3
|
|
- Added support for $display()/$write() and $finish() to Verilog front-end
|
|
- Added "yosys-smtbmc" formal verification flow
|
|
- Added options for clang sanitizers to Makefile
|
|
|
|
* New commands and options
|
|
- Added "scc -expect <N> -nofeedback"
|
|
- Added "proc_dlatch"
|
|
- Added "check"
|
|
- Added "select %xe %cie %coe %M %C %R"
|
|
- Added "sat -dump_json" (WaveJSON format)
|
|
- Added "sat -tempinduct-baseonly -tempinduct-inductonly"
|
|
- Added "sat -stepsize" and "sat -tempinduct-step"
|
|
- Added "sat -show-regs -show-public -show-all"
|
|
- Added "write_json" (Native Yosys JSON format)
|
|
- Added "write_blif -attr"
|
|
- Added "dffinit"
|
|
- Added "chparam"
|
|
- Added "muxcover"
|
|
- Added "pmuxtree"
|
|
- Added memory_bram "make_outreg" feature
|
|
- Added "splice -wires"
|
|
- Added "dff2dffe -direct-match"
|
|
- Added simplemap $lut support
|
|
- Added "read_blif"
|
|
- Added "opt_share -share_all"
|
|
- Added "aigmap"
|
|
- Added "write_smt2 -mem -regs -wires"
|
|
- Added "memory -nordff"
|
|
- Added "write_smv"
|
|
- Added "synth -nordff -noalumacc"
|
|
- Added "rename -top new_name"
|
|
- Added "opt_const -clkinv"
|
|
- Added "synth -nofsm"
|
|
- Added "miter -assert"
|
|
- Added "read_verilog -noautowire"
|
|
- Added "read_verilog -nodpi"
|
|
- Added "tribuf"
|
|
- Added "lut2mux"
|
|
- Added "nlutmap"
|
|
- Added "qwp"
|
|
- Added "test_cell -noeval"
|
|
- Added "edgetypes"
|
|
- Added "equiv_struct"
|
|
- Added "equiv_purge"
|
|
- Added "equiv_mark"
|
|
- Added "equiv_add -try -cell"
|
|
- Added "singleton"
|
|
- Added "abc -g -luts"
|
|
- Added "torder"
|
|
- Added "write_blif -cname"
|
|
- Added "submod -copy"
|
|
- Added "dffsr2dff"
|
|
- Added "stat -liberty"
|
|
|
|
* Synthesis metacommands
|
|
- Various improvements in synth_xilinx
|
|
- Added synth_ice40 and synth_greenpak4
|
|
- Added "prep" metacommand for "synthesis lite"
|
|
|
|
* Cell library changes
|
|
- Added cell types to "help" system
|
|
- Added $meminit cell type
|
|
- Added $assume cell type
|
|
- Added $_MUX4_, $_MUX8_, and $_MUX16_ cells
|
|
- Added $tribuf and $_TBUF_ cell types
|
|
- Added read-enable to memory model
|
|
|
|
* YosysJS
|
|
- Various improvements in emscripten build
|
|
- Added alternative webworker-based JS API
|
|
- Added a few example applications
|
|
|
|
|
|
Yosys 0.4 .. Yosys 0.5
|
|
----------------------
|
|
|
|
* API changes
|
|
- Added log_warning()
|
|
- Added eval_select_args() and eval_select_op()
|
|
- Added cell->known(), cell->input(portname), cell->output(portname)
|
|
- Skip blackbox modules in design->selected_modules()
|
|
- Replaced std::map<> and std::set<> with dict<> and pool<>
|
|
- New SigSpec::extend() is what used to be SigSpec::extend_u0()
|
|
- Added YS_OVERRIDE, YS_FINAL, YS_ATTRIBUTE, YS_NORETURN
|
|
|
|
* Cell library changes
|
|
- Added flip-flops with enable ($dffe etc.)
|
|
- Added $equiv cells for equivalence checking framework
|
|
|
|
* Various
|
|
- Updated ABC to hg rev 61ad5f908c03
|
|
- Added clock domain partitioning to ABC pass
|
|
- Improved plugin building (see "yosys-config --build")
|
|
- Added ENABLE_NDEBUG Makefile flag for high-performance builds
|
|
- Added "yosys -d", "yosys -L" and other driver improvements
|
|
- Added support for multi-bit (array) cell ports to "write_edif"
|
|
- Now printing most output to stdout, not stderr
|
|
- Added "onehot" attribute (set by "fsm_map")
|
|
- Various performance improvements
|
|
- Vastly improved Xilinx flow
|
|
- Added "make unsintall"
|
|
|
|
* Equivalence checking
|
|
- Added equivalence checking commands:
|
|
equiv_make equiv_simple equiv_status
|
|
equiv_induct equiv_miter
|
|
equiv_add equiv_remove
|
|
|
|
* Block RAM support:
|
|
- Added "memory_bram" command
|
|
- Added BRAM support to Xilinx flow
|
|
|
|
* Other New Commands and Options
|
|
- Added "dff2dffe"
|
|
- Added "fsm -encfile"
|
|
- Added "dfflibmap -prepare"
|
|
- Added "write_blid -unbuf -undef -blackbox"
|
|
- Added "write_smt2" for writing SMT-LIBv2 files
|
|
- Added "test_cell -w -muxdiv"
|
|
- Added "select -read"
|
|
|
|
|
|
Yosys 0.3.0 .. Yosys 0.4
|
|
------------------------
|
|
|
|
* Platform Support
|
|
- Added support for mxe-based cross-builds for win32
|
|
- Added sourcecode-export as VisualStudio project
|
|
- Added experimental EMCC (JavaScript) support
|
|
|
|
* Verilog Frontend
|
|
- Added -sv option for SystemVerilog (and automatic *.sv file support)
|
|
- Added support for real-valued constants and constant expressions
|
|
- Added support for non-standard "via_celltype" attribute on task/func
|
|
- Added support for non-standard "module mod_name(...);" syntax
|
|
- Added support for non-standard """ macro bodies
|
|
- Added support for array with more than one dimension
|
|
- Added support for $readmemh and $readmemb
|
|
- Added support for DPI functions
|
|
|
|
* Changes in internal cell library
|
|
- Added $shift and $shiftx cell types
|
|
- Added $alu, $lcu, $fa and $macc cell types
|
|
- Removed $bu0 and $safe_pmux cell types
|
|
- $mem/$memwr WR_EN input is now a per-data-bit enable signal
|
|
- Added $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
|
|
- Renamed ports of $lut cells (from I->O to A->Y)
|
|
- Renamed $_INV_ to $_NOT_
|
|
|
|
* Changes for simple synthesis flows
|
|
- There is now a "synth" command with a recommended default script
|
|
- Many improvements in synthesis of arithmetic functions to gates
|
|
- Multipliers and adders with many operands are using carry-save adder trees
|
|
- Remaining adders are now implemented using Brent-Kung carry look-ahead adders
|
|
- Various new high-level optimizations on RTL netlist
|
|
- Various improvements in FSM optimization
|
|
- Updated ABC to hg 5b5af75f1dda (from 2014-11-07)
|
|
|
|
* Changes in internal APIs and RTLIL
|
|
- Added log_id() and log_cell() helper functions
|
|
- Added function-like cell creation helpers
|
|
- Added GetSize() function (like .size() but with int)
|
|
- Major refactoring of RTLIL::Module and related classes
|
|
- Major refactoring of RTLIL::SigSpec and related classes
|
|
- Now RTLIL::IdString is essentially an int
|
|
- Added macros for code coverage counters
|
|
- Added some Makefile magic for pretty make logs
|
|
- Added "kernel/yosys.h" with all the core definitions
|
|
- Changed a lot of code from FILE* to c++ streams
|
|
- Added RTLIL::Monitor API and "trace" command
|
|
- Added "Yosys" C++ namespace
|
|
|
|
* Changes relevant to SAT solving
|
|
- Added ezSAT::keep_cnf() and ezSAT::non_incremental()
|
|
- Added native ezSAT support for vector shift ops
|
|
- Updated MiniSAT to git 37dc6c67e2 (from 2013-09-25)
|
|
|
|
* New commands (or large improvements to commands)
|
|
- Added "synth" command with default script
|
|
- Added "share" (finally some real resource sharing)
|
|
- Added "memory_share" (reduce number of ports on memories)
|
|
- Added "wreduce" and "alumacc" commands
|
|
- Added "opt -keepdc -fine -full -fast"
|
|
- Added some "test_*" commands
|
|
|
|
* Various other changes
|
|
- Added %D and %c select operators
|
|
- Added support for labels in yosys scripts
|
|
- Added support for here-documents in yosys scripts
|
|
- Support "+/" prefix for files from proc_share_dir
|
|
- Added "autoidx" statement to ilang language
|
|
- Switched from "yosys-svgviewer" to "xdot"
|
|
- Renamed "stdcells.v" to "techmap.v"
|
|
- Various bug fixes and small improvements
|
|
- Improved welcome and bye messages
|
|
|
|
|
|
Yosys 0.2.0 .. Yosys 0.3.0
|
|
--------------------------
|
|
|
|
* Driver program and overall behavior:
|
|
- Added "design -push" and "design -pop"
|
|
- Added "tee" command for redirecting log output
|
|
|
|
* Changes in the internal cell library:
|
|
- Added $dlatchsr and $_DLATCHSR_???_ cell types
|
|
|
|
* Improvements in Verilog frontend:
|
|
- Improved support for const functions (case, always, repeat)
|
|
- The generate..endgenerate keywords are now optional
|
|
- Added support for arrays of module instances
|
|
- Added support for "`default_nettype" directive
|
|
- Added support for "`line" directive
|
|
|
|
* Other front- and back-ends:
|
|
- Various changes to "write_blif" options
|
|
- Various improvements in EDIF backend
|
|
- Added "vhdl2verilog" pseudo-front-end
|
|
- Added "verific" pseudo-front-end
|
|
|
|
* Improvements in technology mapping:
|
|
- Added support for recursive techmap
|
|
- Added CONSTMSK and CONSTVAL features to techmap
|
|
- Added _TECHMAP_CONNMAP_*_ feature to techmap
|
|
- Added _TECHMAP_REPLACE_ feature to techmap
|
|
- Added "connwrappers" command for wrap-extract-unwrap method
|
|
- Added "extract -map %<design_name>" feature
|
|
- Added "extract -ignore_param ..." and "extract -ignore_parameters"
|
|
- Added "techmap -max_iter" option
|
|
|
|
* Improvements to "eval" and "sat" framework:
|
|
- Now include a copy of Minisat (with build fixes applied)
|
|
- Switched to Minisat::SimpSolver as SAT back-end
|
|
- Added "sat -dump_vcd" feature
|
|
- Added "sat -dump_cnf" feature
|
|
- Added "sat -initsteps <N>" feature
|
|
- Added "freduce -stop <N>" feature
|
|
- Added "freduce -dump <prefix>" feature
|
|
|
|
* Integration with ABC:
|
|
- Updated ABC rev to 7600ffb9340c
|
|
|
|
* Improvements in the internal APIs:
|
|
- Added RTLIL::Module::add... helper methods
|
|
- Various build fixes for OSX (Darwin) and OpenBSD
|
|
|
|
|
|
Yosys 0.1.0 .. Yosys 0.2.0
|
|
--------------------------
|
|
|
|
* Changes to the driver program:
|
|
- Added "yosys -h" and "yosys -H"
|
|
- Added support for backslash line continuation in scripts
|
|
- Added support for #-comments in same line as command
|
|
- Added "echo" and "log" commands
|
|
|
|
* Improvements in Verilog frontend:
|
|
- Added support for local registers in named blocks
|
|
- Added support for "case" in "generate" blocks
|
|
- Added support for $clog2 system function
|
|
- Added support for basic SystemVerilog assert statements
|
|
- Added preprocessor support for macro arguments
|
|
- Added preprocessor support for `elsif statement
|
|
- Added "verilog_defaults" command
|
|
- Added read_verilog -icells option
|
|
- Added support for constant sizes from parameters
|
|
- Added "read_verilog -setattr"
|
|
- Added support for function returning 'integer'
|
|
- Added limited support for function calls in parameter values
|
|
- Added "read_verilog -defer" to suppress evaluation of modules with default parameters
|
|
|
|
* Other front- and back-ends:
|
|
- Added BTOR backend
|
|
- Added Liberty frontend
|
|
|
|
* Improvements in technology mapping:
|
|
- The "dfflibmap" command now strongly prefers solutions with
|
|
no inverters in clock paths
|
|
- The "dfflibmap" command now prefers cells with smaller area
|
|
- Added support for multiple -map options to techmap
|
|
- Added "dfflibmap" support for //-comments in liberty files
|
|
- Added "memory_unpack" command to revert "memory_collect"
|
|
- Added standard techmap rule "techmap -share_map pmux2mux.v"
|
|
- Added "iopadmap -bits"
|
|
- Added "setundef" command
|
|
- Added "hilomap" command
|
|
|
|
* Changes in the internal cell library:
|
|
- Major rewrite of simlib.v for better compatibility with other tools
|
|
- Added PRIORITY parameter to $memwr cells
|
|
- Added TRANSPARENT parameter to $memrd cells
|
|
- Added RD_TRANSPARENT parameter to $mem cells
|
|
- Added $bu0 cell (always 0-extend, even undef MSB)
|
|
- Added $assert cell type
|
|
- Added $slice and $concat cell types
|
|
|
|
* Integration with ABC:
|
|
- Updated ABC to hg rev 2058c8ccea68
|
|
- Tighter integration of ABC build with Yosys build. The make
|
|
targets 'make abc' and 'make install-abc' are now obsolete.
|
|
- Added support for passing FFs from one clock domain through ABC
|
|
- Now always use BLIF as exchange format with ABC
|
|
- Added support for "abc -script +<command_sequence>"
|
|
- Improved standard ABC recipe
|
|
- Added support for "keep" attribute to abc command
|
|
- Added "abc -dff / -clk / -keepff" options
|
|
|
|
* Improvements to "eval" and "sat" framework:
|
|
- Added support for "0" and "~0" in right-hand side -set expressions
|
|
- Added "eval -set-undef" and "eval -table"
|
|
- Added "sat -set-init" and "sat -set-init-*" for sequential problems
|
|
- Added undef support to SAT solver, incl. various new "sat" options
|
|
- Added correct support for === and !== for "eval" and "sat"
|
|
- Added "sat -tempinduct" (default -seq is now non-induction sequential)
|
|
- Added "sat -prove-asserts"
|
|
- Complete rewrite of the 'freduce' command
|
|
- Added "miter" command
|
|
- Added "sat -show-inputs" and "sat -show-outputs"
|
|
- Added "sat -ignore_unknown_cells" (now produce an error by default)
|
|
- Added "sat -falsify"
|
|
- Now "sat -verify" and "sat -falsify" can also be used without "-prove"
|
|
- Added "expose" command
|
|
- Added support for @<sel_name> to sat and eval signal expressions
|
|
|
|
* Changes in the 'make test' framework and auxiliary test tools:
|
|
- Added autotest.sh -p and -f options
|
|
- Replaced autotest.sh ISIM support with XSIM support
|
|
- Added test cases for SAT framework
|
|
|
|
* Added "abbreviated IDs":
|
|
- Now $<something>$foo can be abbreviated as $foo.
|
|
- Usually this last part is a unique id (from RTLIL::autoidx)
|
|
- This abbreviated IDs are now also used in "show" output
|
|
|
|
* Other changes to selection framework:
|
|
- Now */ is optional in */<mode>:<arg> expressions
|
|
- Added "select -assert-none" and "select -assert-any"
|
|
- Added support for matching modules by attribute (A:<expr>)
|
|
- Added "select -none"
|
|
- Added support for r:<expr> pattern for matching cell parameters
|
|
- Added support for !=, <, <=, >=, > for attribute and parameter matching
|
|
- Added support for %s for selecting sub-modules
|
|
- Added support for %m for expanding selections to whole modules
|
|
- Added support for i:*, o:* and x:* pattern for selecting module ports
|
|
- Added support for s:<expr> pattern for matching wire width
|
|
- Added support for %a operation to select wire aliases
|
|
|
|
* Various other changes to commands and options:
|
|
- The "ls" command now supports wildcards
|
|
- Added "show -pause" and "show -format dot"
|
|
- Added "show -color" support for cells
|
|
- Added "show -label" and "show -notitle"
|
|
- Added "dump -m" and "dump -n"
|
|
- Added "history" command
|
|
- Added "rename -hide"
|
|
- Added "connect" command
|
|
- Added "splitnets -driver"
|
|
- Added "opt_const -mux_undef"
|
|
- Added "opt_const -mux_bool"
|
|
- Added "opt_const -undriven"
|
|
- Added "opt -mux_undef -mux_bool -undriven -purge"
|
|
- Added "hierarchy -libdir"
|
|
- Added "hierarchy -purge_lib" (by default now do not remove lib cells)
|
|
- Added "delete" command
|
|
- Added "dump -append"
|
|
- Added "setattr" and "setparam" commands
|
|
- Added "design -stash/-copy-from/-copy-to"
|
|
- Added "copy" command
|
|
- Added "splice" command
|
|
|