Marcelina Kościelnicka 0aad88a2fb Add clean_zerowidth pass, use it for Verilog output. ... This should remove instances of zero-width sigspecs in the netlist, avoiding problems in the Verilog backend with emitting them. See #3103.		2021-12-12 19:56:50 +01:00
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cmds	Add clean_zerowidth pass, use it for Verilog output.	2021-12-12 19:56:50 +01:00
equiv	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
fsm	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
hierarchy	verilog: use derived module info to elaborate cell connections	2021-10-25 18:25:50 -07:00
memory	FfData: some refactoring.	2021-10-07 04:24:06 +02:00
opt	opt_mem_priority: Fix non-ascii char in help message.	2021-12-09 00:56:14 +01:00
pmgen	Make it work on all	2021-11-05 10:51:58 +01:00
proc	proc_dff: Emit $aldff.	2021-10-27 14:14:24 +02:00
sat	FfData: some refactoring.	2021-10-07 04:24:06 +02:00
techmap	sta: very crude static timing analysis pass	2021-11-25 17:20:27 +01:00
tests	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00