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https://github.com/YosysHQ/yosys
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1248af1e02
Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
17 lines
359 B
Text
17 lines
359 B
Text
read_verilog -sv <<EOF
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module top;
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parameter AVOID_LATCH = 0;
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logic x, z;
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assign z = 1'b1;
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always_comb begin
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logic y;
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if (z)
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y = 0;
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for (int i = 1; i == AVOID_LATCH; i++)
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y = 1;
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x = z ? y : 1'b0;
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end
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endmodule
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EOF
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logger -expect error '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y. from always_comb process' 1
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proc
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