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https://github.com/YosysHQ/yosys
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1248af1e02
Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.
79 lines
1.6 KiB
Text
79 lines
1.6 KiB
Text
read_rtlil << EOT
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module \top
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wire input 1 \A
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wire output 2 \Y
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cell \sg13g2_and2_1 \sub
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connect \A \A
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connect \B 1'0
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connect \Y \Y
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end
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end
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EOT
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logger -expect log 'Chip area for module .\\top.: 9.072000' 1
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logger -expect-no-warnings
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logger -expect log " 1 9.072 cells" 1
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logger -expect log " 1 9.072 sg13g2_and2_1" 1
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stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz
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design -reset
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read_rtlil << EOT
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module \top
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wire input 1 \A
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wire output 2 \Y
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wire output 3 \N
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cell \sg13g2_and2_1 \sub1
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connect \A \A
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connect \B 1'0
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connect \Y \Y
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end
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cell \child \sequential
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connect \A \A
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connect \B 1'0
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connect \R 1'0
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connect \Y \Y
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connect \N \N
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end
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cell \child \sequential1
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connect \A \A
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connect \B 1'0
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connect \R 1'0
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connect \Y \Y
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connect \N \N
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end
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cell \sg13g2_and2_1 \sub2
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connect \A \A
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connect \B 1'0
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connect \Y \Y
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end
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end
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module \child
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wire input 1 \A
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wire input 2 \B
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wire input 3 \R
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wire output 4 \Y
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wire output 5 \N
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cell \sg13g2_dfrbp_1 \sequential_ff
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connect \CLK \A
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connect \D \B
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connect \Q \Y
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connect \Q_N \N
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connect \RESET_B \R
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end
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end
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EOT
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logger -expect log 'Chip area for top module .\\top.: 112.492800' 1
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logger -expect log "of which used for sequential elements: 94.348800" 1
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logger -expect log "2 18.144 cells" 1
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logger -expect log "4 112.493 cells" 1
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logger -expect log "2 94.349 sg13g2_dfrbp_1" 1
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logger -expect-no-warnings
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stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz -top \top
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