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yosys/tests/verilog/genblk_wire.ys
Yannick Lamarre 54b278d574 Add tests for implicit wires in generate blocks.
Signed-off-by: Yannick Lamarre <yan.lamarre@gmail.com>
2025-12-10 14:43:42 +01:00

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logger -expect warning "Identifier `\\genblk1[[]0[]]\.x' is implicitly declared." 1
logger -expect warning "Identifier `\\genblk1[[]1[]]\.x' is implicitly declared." 1
read_verilog -sv genblk_wire.sv
logger -check-expected
select -assert-count 1 gate/genblk1[0].x
select -assert-count 1 gate/genblk1[1].x
select -assert-count 0 gate/genblk1[2].x
select -assert-count 1 gold/genblk1[0].x
select -assert-count 1 gold/genblk1[1].x
select -assert-count 0 gold/genblk1[2].x
proc
equiv_make gold gate equiv
equiv_simple
equiv_status -assert