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11 lines
207 B
Verilog
11 lines
207 B
Verilog
module module_scope_case_top(
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input wire x,
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output reg y
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);
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always @* begin
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case (module_scope_case_top.x)
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1: module_scope_case_top.y = 0;
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0: module_scope_case_top.y = 1;
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endcase
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end
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endmodule
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