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Co-authored-by: Claire Xenia Wolf <claire@clairexen.net> Signed-off-by: gatecat <gatecat@ds0.me>
4 lines
180 B
Verilog
4 lines
180 B
Verilog
// Any inverters not folded into LUTs are mapped to a LUT of their own
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module \$__CC_NOT (input A, output Y);
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CC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y));
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endmodule
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