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16 lines
299 B
Verilog
16 lines
299 B
Verilog
(* techmap_celltype = "$dff" *)
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module dff2ff (CLK, D, Q);
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parameter WIDTH = 1;
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parameter CLK_POLARITY = 1;
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input CLK;
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(* force_downto *)
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input [WIDTH-1:0] D;
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(* force_downto *)
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output reg [WIDTH-1:0] Q;
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wire [1023:0] _TECHMAP_DO_ = "proc;;";
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always @($global_clock)
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Q <= D;
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endmodule
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