mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
8 lines
142 B
Verilog
8 lines
142 B
Verilog
module uut(in1, in2, in3, out1, out2);
|
|
|
|
input [8:0] in1, in2, in3;
|
|
output [8:0] out1, out2;
|
|
|
|
assign out1 = in1 + in2 + (in3 >> 4);
|
|
|
|
endmodule
|