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b14a651142
Link to verilator in the introduction. Include `verilator --lint-only fifo.v` in the example synth doc. Fix linter warnings in fifo.v.
71 lines
1.3 KiB
Verilog
71 lines
1.3 KiB
Verilog
// address generator/counter
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module addr_gen
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#( parameter MAX_DATA=256,
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localparam AWIDTH = $clog2(MAX_DATA)
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) ( input en, clk, rst,
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output reg [AWIDTH-1:0] addr
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);
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initial addr = 0;
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// async reset
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// increment address when enabled
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always @(posedge clk or posedge rst)
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if (rst)
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addr <= 0;
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else if (en) begin
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if ({'0, addr} == MAX_DATA-1)
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addr <= 0;
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else
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addr <= addr + 1;
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end
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endmodule //addr_gen
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// Define our top level fifo entity
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module fifo
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#( parameter MAX_DATA=256,
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localparam AWIDTH = $clog2(MAX_DATA)
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) ( input wen, ren, clk, rst,
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input [7:0] wdata,
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output reg [7:0] rdata,
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output reg [AWIDTH:0] count
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);
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// fifo storage
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// sync read before write
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wire [AWIDTH-1:0] waddr, raddr;
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reg [7:0] data [MAX_DATA-1:0];
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always @(posedge clk) begin
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if (wen)
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data[waddr] <= wdata;
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rdata <= data[raddr];
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end // storage
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// addr_gen for both write and read addresses
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addr_gen #(.MAX_DATA(MAX_DATA))
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fifo_writer (
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.en (wen),
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.clk (clk),
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.rst (rst),
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.addr (waddr)
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);
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addr_gen #(.MAX_DATA(MAX_DATA))
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fifo_reader (
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.en (ren),
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.clk (clk),
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.rst (rst),
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.addr (raddr)
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);
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// status signals
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initial count = 0;
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always @(posedge clk or posedge rst) begin
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if (rst)
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count <= 0;
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else if (wen && !ren)
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count <= count + 1;
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else if (ren && !wen)
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count <= count - 1;
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end
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endmodule
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