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https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
27 lines
674 B
Verilog
27 lines
674 B
Verilog
module axis_master(aclk, aresetn, tvalid, tready, tdata);
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input aclk, aresetn, tready;
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output reg tvalid;
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output reg [7:0] tdata;
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reg [31:0] state;
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always @(posedge aclk) begin
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if (!aresetn) begin
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state <= 314159265;
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tvalid <= 0;
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tdata <= 'bx;
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end else begin
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if (tvalid && tready)
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tvalid <= 0;
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if (!tvalid || !tready) begin
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// ^- should not be inverted!
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state = state ^ state << 13;
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state = state ^ state >> 7;
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state = state ^ state << 17;
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if (state[9:8] == 0) begin
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tvalid <= 1;
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tdata <= state;
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end
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end
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end
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end
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endmodule
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