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105 lines
1.9 KiB
Verilog
105 lines
1.9 KiB
Verilog
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module dff(clk, d, q);
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input clk, d;
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output reg q;
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always @(posedge clk)
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q <= d;
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endmodule
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module dffa(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or posedge arst) begin
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if (arst)
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q <= 1;
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else
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q <= d;
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end
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endmodule
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module dffa1(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or negedge arst) begin
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if (~arst)
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q <= 0;
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else
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q <= d;
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end
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endmodule
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module dffa2(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or negedge arst) begin
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if (!arst)
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q <= 0;
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else
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q <= d;
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end
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endmodule
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module dffa3(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk or negedge arst) begin
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if (~(!arst))
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q <= d;
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else
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q <= 1;
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end
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endmodule
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module dffa4(clk, arst1, arst2, arst3, d, q);
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input clk, arst1, arst2, arst3, d;
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output reg q;
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always @(posedge clk, posedge arst1, posedge arst2, negedge arst3) begin
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if (arst1)
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q <= 0;
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else if (arst2)
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q <= 0;
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else if (!arst3)
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q <= 0;
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else
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q <= d;
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end
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endmodule
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// SR-Flip-Flops are on the edge of well defined Verilog constructs in terms of
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// simulation-implementation mismatches. The following testcases try to cover the
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// part that is defined and avoid the undefined cases.
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module dffsr1(clk, arst, d, q);
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input clk, arst, d;
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output reg q;
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always @(posedge clk, posedge arst) begin
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if (arst)
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q <= d^d; // constant expression -- but the frontend optimizer does not know that..
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else
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q <= d;
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end
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endmodule
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module dffsr2(clk, preset, clear, d, q);
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input clk, preset, clear, d;
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output q;
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(* gentb_clock *)
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wire clk, preset, clear, d;
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dffsr2_sub uut (clk, preset && !clear, !preset && clear, d, q);
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endmodule
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(* gentb_skip *)
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module dffsr2_sub(clk, preset, clear, d, q);
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input clk, preset, clear, d;
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output reg q;
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always @(posedge clk, posedge preset, posedge clear) begin
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if (preset)
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q <= 1;
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else if (clear)
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q <= 0;
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else
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q <= d;
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end
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endmodule
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