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https://github.com/YosysHQ/yosys
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13 lines
264 B
Makefile
13 lines
264 B
Makefile
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demo1: demo1.smt2
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yosys-smtbmc -c demo1.vcd demo1.smt2
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yosys-smtbmc -i -c demo1.vcd demo1.smt2
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demo1.smt2: demo1.v
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yosys -p 'read_verilog -formal demo1.v; prep -top demo1; write_smt2 -wires -mem -bv demo1.smt2'
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clean:
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rm -f demo1.smt2
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.PHONY: demo1 clean
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