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https://github.com/YosysHQ/yosys
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fc1c9aa11f
Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
26 lines
852 B
Text
26 lines
852 B
Text
# This file contains the names of verilog files to exclude from verilog to FIRRTL regression tests due to known failures.
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arraycells.v inst id[0] of
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dff_different_styles.v
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generate.v combinational loop
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hierdefparam.v inst id[0] of
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i2c_master_tests.v $adff
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macros.v drops modules
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mem2reg.v drops modules
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mem_arst.v $adff
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memory.v $adff
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multiplier.v inst id[0] of
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muxtree.v drops modules
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omsp_dbg_uart.v $adff
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operators.v $pow
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paramods.v subfield assignment (bits() <= ...)
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partsel.v drops modules
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process.v drops modules
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realexpr.v drops modules
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scopes.v original verilog issues ( -x where x isn't declared signed)
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sincos.v $adff
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specify.v no code (empty module generates error
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subbytes.v $adff
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task_func.v drops modules
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values.v combinational loop
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vloghammer.v combinational loop
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wreduce.v original verilog issues ( -x where x isn't declared signed)
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