Zachary Snow 0d8e5d965f Sign extend port connections where necessary ... - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265		2020-12-18 20:33:14 -07:00
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ast.cc	Return correct modname when found in cache.	2020-11-26 13:31:22 +01:00
ast.h	Added $high(), $low(), $left(), $right()	2020-09-15 20:49:52 +03:00
dpicall.cc	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
genrtlil.cc	Sign extend port connections where necessary	2020-12-18 20:33:14 -07:00
Makefile.inc	Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)	2014-08-21 12:43:51 +02:00
simplify.cc	Merge pull request #2378 from udif/pr_dollar_high_low	2020-10-01 18:17:36 +02:00