mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 20:38:44 +00:00
11 lines
227 B
Plaintext
11 lines
227 B
Plaintext
read_verilog test_arith.v
|
|
synth_ice40
|
|
techmap -map ../cells_sim.v
|
|
rename test gate
|
|
|
|
read_verilog test_arith.v
|
|
rename test gold
|
|
|
|
miter -equiv -flatten -make_outputs gold gate miter
|
|
sat -verify -prove trigger 0 -show-ports miter
|