yosys/tests/verilog/for_decl_shadow.ys at df2bbe0bb5cde9b1ec07e3496296446bff425b2f - mirrors/yosys - Libre-Chip.org

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Zachary Snow f0a52e3dd2 sv: support declaration in procedural for initialization

In line with other tools, this adds an extra wrapping block around such
for loops to appropriately scope the variable.

2021-08-30 15:19:21 -06:00

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 read_verilog -sv for_decl_shadow.sv
 hierarchy
 proc
 equiv_make gold gate equiv
 equiv_simple
 equiv_status -assert