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12 lines
217 B
Text
12 lines
217 B
Text
read_verilog <<EOT
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module top(input clk, pre, d, output reg q);
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always @(posedge clk, posedge pre)
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if (pre)
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q <= 1'b1;
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else
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q <= d;
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endmodule
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EOT
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prep
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equiv_opt -assert -multiclock -map +/simcells.v synth
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