mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
cf60699884
The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
16 lines
582 B
Text
16 lines
582 B
Text
read_verilog ../common/fsm.v
|
|
hierarchy -top fsm
|
|
proc
|
|
flatten
|
|
|
|
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
|
|
miter -equiv -make_assert -flatten gold gate miter
|
|
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
|
|
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd fsm # Constrain all select calls below inside the top module
|
|
|
|
select -assert-count 4 t:SB_DFF
|
|
select -assert-count 2 t:SB_DFFESR
|
|
select -assert-max 15 t:SB_LUT4
|
|
select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D
|