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105 lines
3.7 KiB
ReStructuredText
105 lines
3.7 KiB
ReStructuredText
.. role:: verilog(code)
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:language: Verilog
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Latch cells
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-----------
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The cell types `$_DLATCH_N_` and `$_DLATCH_P_` represent d-type latches.
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.. table:: Cell types for basic latches
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======================================= =============
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Verilog Cell Type
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======================================= =============
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:verilog:`always @* if (!E) Q <= D` `$_DLATCH_N_`
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:verilog:`always @* if (E) Q <= D` `$_DLATCH_P_`
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======================================= =============
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The cell types ``$_DLATCH_[NP][NP][01]_`` implement d-type latches with reset.
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The values in the table for these cell types relate to the following Verilog
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code template:
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.. code-block:: verilog
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:force:
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always @*
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if (R == RST_LVL)
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Q <= RST_VAL;
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else if (E == EN_LVL)
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Q <= D;
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.. table:: Cell types for gate level logic networks (latches with reset)
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:name: tab:CellLib_gates_adlatch
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============= ============== ============== ===============
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:math:`EnLvl` :math:`RstLvl` :math:`RstVal` Cell Type
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============= ============== ============== ===============
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``0`` ``0`` ``0`` `$_DLATCH_NN0_`
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``0`` ``0`` ``1`` `$_DLATCH_NN1_`
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``0`` ``1`` ``0`` `$_DLATCH_NP0_`
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``0`` ``1`` ``1`` `$_DLATCH_NP1_`
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``1`` ``0`` ``0`` `$_DLATCH_PN0_`
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``1`` ``0`` ``1`` `$_DLATCH_PN1_`
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``1`` ``1`` ``0`` `$_DLATCH_PP0_`
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``1`` ``1`` ``1`` `$_DLATCH_PP1_`
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============= ============== ============== ===============
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The cell types ``$_DLATCHSR_[NP][NP][NP]_`` implement d-type latches with set
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and reset. The values in the table for these cell types relate to the following
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Verilog code template:
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.. code-block:: verilog
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:force:
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always @*
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if (R == RST_LVL)
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Q <= 0;
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else if (S == SET_LVL)
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Q <= 1;
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else if (E == EN_LVL)
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Q <= D;
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.. table:: Cell types for gate level logic networks (latches with set and reset)
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:name: tab:CellLib_gates_dlatchsr
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============= ============== ============== =================
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:math:`EnLvl` :math:`SetLvl` :math:`RstLvl` Cell Type
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============= ============== ============== =================
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``0`` ``0`` ``0`` `$_DLATCHSR_NNN_`
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``0`` ``0`` ``1`` `$_DLATCHSR_NNP_`
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``0`` ``1`` ``0`` `$_DLATCHSR_NPN_`
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``0`` ``1`` ``1`` `$_DLATCHSR_NPP_`
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``1`` ``0`` ``0`` `$_DLATCHSR_PNN_`
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``1`` ``0`` ``1`` `$_DLATCHSR_PNP_`
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``1`` ``1`` ``0`` `$_DLATCHSR_PPN_`
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``1`` ``1`` ``1`` `$_DLATCHSR_PPP_`
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============= ============== ============== =================
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The cell types ``$_SR_[NP][NP]_`` implement sr-type latches. The values in the
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table for these cell types relate to the following Verilog code template:
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.. code-block:: verilog
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:force:
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always @*
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if (R == RST_LVL)
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Q <= 0;
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else if (S == SET_LVL)
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Q <= 1;
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.. table:: Cell types for gate level logic networks (SR latches)
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:name: tab:CellLib_gates_sr
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============== ============== ==========
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:math:`SetLvl` :math:`RstLvl` Cell Type
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============== ============== ==========
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``0`` ``0`` `$_SR_NN_`
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``0`` ``1`` `$_SR_NP_`
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``1`` ``0`` `$_SR_PN_`
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``1`` ``1`` `$_SR_PP_`
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============== ============== ==========
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.. autocellgroup:: reg_latch
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:members:
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:source:
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:linenos:
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