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yosys/techlibs/xilinx
Clifford Wolf bfcd46dbd3
Merge pull request #842 from litghost/merge_upstream
Changes required for VPR place and route in synth_xilinx
2019-03-05 15:33:19 -08:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_bb.v
brams_init.py
brams_map.v
cells_map.v
cells_sim.v
cells_xtra.sh
cells_xtra.v
drams.txt
drams_map.v
ff_map.v
lut_map.v
Makefile.inc
synth_xilinx.cc Merge pull request #842 from litghost/merge_upstream 2019-03-05 15:33:19 -08:00