mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-13 04:28:18 +00:00
492 lines
11 KiB
Plaintext
492 lines
11 KiB
Plaintext
pattern xilinx_dsp
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state <std::function<SigSpec(const SigSpec&)>> unextend
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state <SigBit> clock
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state <SigSpec> sigA sigffAmuxY sigB sigffBmuxY sigC sigffCmuxY sigD sigffDmuxY sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <bool> ffAcepol ffADcepol ffBcepol ffCcepol ffDcepol ffMcepol ffMrstpol ffPcepol ffPrstpol
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state <int> ffPoffset
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state <Cell*> ffAD ffADmux ffA ffAmux ffB ffBmux ffC ffCmux ffD ffDmux ffM ffMcemux ffMrstmux ffP ffPcemux ffPrstmux
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// subpattern
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state <SigSpec> argQ argD
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state <bool> ffcepol ffrstpol
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state <int> ffoffset
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff dffcemux dffrstmux
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udata <bool> dffcepol dffrstpol
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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code unextend sigA sigB sigC sigD sigM
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unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigA = unextend(port(dsp, \A));
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sigB = unextend(port(dsp, \B));
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sigC = dsp->connections_.at(\C, SigSpec());
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sigD = dsp->connections_.at(\D, SigSpec());
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SigSpec P = port(dsp, \P);
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if (dsp->parameters.at(\USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") {
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// Only care about those bits that are used
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int i;
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for (i = 0; i < GetSize(P); i++) {
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if (nusers(P[i]) <= 1)
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break;
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sigM.append(P[i]);
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}
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log_assert(nusers(P.extract_end(i)) <= 1);
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}
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else
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sigM = P;
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endcode
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code argQ ffAD ffADmux ffADcepol sigA clock
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if (param(dsp, \ADREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffAD = dff;
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clock = dffclock;
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if (dffcemux) {
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ffADmux = dffcemux;
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ffADcepol = dffcepol;
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}
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sigA = dffD;
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}
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}
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endcode
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match preAdd
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if sigD.empty() || sigD.is_fully_zero()
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// Ensure that preAdder not already used
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if dsp->parameters.at(\USE_DPORT, Const("FALSE")).decode_string() == "FALSE"
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if dsp->connections_.at(\INMODE, Const(0, 5)).is_fully_zero()
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select preAdd->type.in($add)
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// Output has to be 25 bits or less
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select GetSize(port(preAdd, \Y)) <= 25
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select nusers(port(preAdd, \Y)) == 2
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choice <IdString> AB {\A, \B}
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// A port has to be 30 bits or less
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select GetSize(port(preAdd, AB)) <= 30
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define <IdString> BA (AB == \A ? \B : \A)
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// D port has to be 25 bits or less
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select GetSize(port(preAdd, BA)) <= 25
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index <SigSpec> port(preAdd, \Y) === sigA
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optional
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endmatch
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code sigA sigD
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if (preAdd) {
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sigA = port(preAdd, \A);
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sigD = port(preAdd, \B);
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if (GetSize(sigA) < GetSize(sigD))
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std::swap(sigA, sigD);
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}
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endcode
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code argQ ffA ffAmux ffAcepol sigA clock ffAD ffADmux ffADcepol
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// Only search for ffA if there was a pre-adder
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// (otherwise ffA would have been matched as ffAD)
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if (preAdd) {
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if (param(dsp, \AREG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA = dff;
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clock = dffclock;
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if (dffcemux) {
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ffAmux = dffcemux;
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ffAcepol = dffcepol;
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}
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sigA = dffD;
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}
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}
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}
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// And if there wasn't a pre-adder,
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// move AD register to A
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else if (ffAD) {
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log_assert(!ffA && !ffAmux);
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std::swap(ffA, ffAD);
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std::swap(ffAmux, ffADmux);
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ffAcepol = ffADcepol;
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}
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endcode
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code argQ ffB ffBmux ffBcepol sigB clock
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if (param(dsp, \BREG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB = dff;
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clock = dffclock;
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if (dffcemux) {
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ffBmux = dffcemux;
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ffBcepol = dffcepol;
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}
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sigB = dffD;
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}
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}
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endcode
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code argQ ffD ffDmux ffDcepol sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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if (dff) {
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ffD = dff;
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clock = dffclock;
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if (dffcemux) {
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ffDmux = dffcemux;
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ffDcepol = dffcepol;
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}
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sigD = dffD;
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}
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}
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endcode
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code argD ffM ffMcemux ffMrstmux ffMcepol ffMrstpol sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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if (dff) {
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ffM = dff;
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clock = dffclock;
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if (dffcemux) {
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ffMcemux = dffcemux;
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ffMrstmux = dffrstmux;
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ffMcepol = dffcepol;
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ffMrstpol = dffrstpol;
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}
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sigM = dffQ;
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}
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}
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sigP = sigM;
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endcode
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match postAdd
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// Ensure that Z mux is not already used
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if port(dsp, \OPMODE).extract(4,3).is_fully_zero()
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select postAdd->type.in($add)
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select GetSize(port(postAdd, \Y)) <= 48
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select nusers(port(postAdd, \Y)) == 2
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) <= 3
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filter ffMcemux || nusers(port(postAdd, AB)) == 2
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filter !ffMcemux || nusers(port(postAdd, AB)) == 3
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filter GetSize(unextend(port(postAdd, AB))) <= GetSize(sigP)
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filter unextend(port(postAdd, AB)) == sigP.extract(0, GetSize(unextend(port(postAdd, AB))))
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filter nusers(sigP.extract_end(GetSize(unextend(port(postAdd, AB))))) <= 1
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set postAddAB AB
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optional
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endmatch
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code sigC sigP
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if (postAdd) {
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sigC = port(postAdd, postAddAB == \A ? \B : \A);
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// TODO for DSP48E1, which will have sign extended inputs/outputs
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//int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
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//int actual_mul_width = GetSize(sigP);
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//int actual_acc_width = GetSize(sigC);
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//if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
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// reject;
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//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(postAdd, \A_SIGNED).as_bool()))
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// reject;
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sigP = port(postAdd, \Y);
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}
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endcode
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code argD ffP ffPcemux ffPrstmux ffPcepol ffPrstpol sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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// If ffMcemux and no postAdd new-value net must have exactly three users: ffMcemux, ffM and ffPcemux
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if ((ffMcemux && !postAdd && nusers(sigP) == 3) ||
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// Otherwise new-value net must have exactly two users: dsp and ffPcemux
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((!ffMcemux || postAdd) && nusers(sigP) == 2)) {
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argD = sigP;
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subpattern(out_dffe);
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if (dff) {
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ffP = dff;
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clock = dffclock;
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if (dffcemux) {
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ffPcemux = dffcemux;
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ffPcepol = dffcepol;
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ffPrstmux = dffrstmux;
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ffPrstpol = dffrstpol;
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}
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sigP = dffQ;
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}
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}
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}
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endcode
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match postAddMux
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if postAdd
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if ffP
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select postAddMux->type.in($mux)
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select nusers(port(postAddMux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(postAddMux, AB) === sigP
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index <SigSpec> port(postAddMux, \Y) === sigC
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set postAddMuxAB AB
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optional
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endmatch
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code sigC
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if (postAddMux)
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code argQ ffC ffCmux ffCcepol sigC clock
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if (param(dsp, \CREG).as_int() == 0) {
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argQ = sigC;
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subpattern(in_dffe);
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if (dff) {
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ffC = dff;
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clock = dffclock;
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if (dffcemux) {
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ffCmux = dffcemux;
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ffCcepol = dffcepol;
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}
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sigC = dffD;
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}
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}
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endcode
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code
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accept;
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endcode
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// #######################
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subpattern in_dffe
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arg argQ clock ffcepol
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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filter GetSize(port(ff, \Q)) >= GetSize(argQ)
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slice offset GetSize(port(ff, \Q))
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filter offset+GetSize(argQ) <= GetSize(port(ff, \Q))
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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semioptional
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endmatch
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code argQ
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if (ff) {
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for (auto c : argQ.chunks())
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if (c.wire->get_bool_attribute(\keep))
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reject;
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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reject;
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}
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dffclock = port(ff, \CLK);
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dff = ff;
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dffD = argQ;
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dffD.replace(port(ff, \Q), port(ff, \D));
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// Only search for ffcemux if argQ has at
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// least 3 users (ff, <upstream>, ffcemux) and
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// its ff.D only has two (ff, ffcemux)
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if (!(nusers(argQ) >= 3 && nusers(dffD) == 2))
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argQ = SigSpec();
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}
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else {
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dff = nullptr;
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argQ = SigSpec();
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}
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endcode
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match ffcemux
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if !argQ.empty()
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select ffcemux->type.in($mux)
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index <SigSpec> port(ffcemux, \Y) === port(ff, \D)
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filter GetSize(port(ffcemux, \Y)) >= GetSize(dffD)
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slice offset GetSize(port(ffcemux, \Y))
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filter offset+GetSize(dffD) <= GetSize(port(ffcemux, \Y))
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filter port(ffcemux, \Y).extract(offset, GetSize(dffD)) == dffD
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choice <IdString> AB {\A, \B}
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filter offset+GetSize(argQ) <= GetSize(port(ffcemux, \Y))
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filter port(ffcemux, AB).extract(offset, GetSize(argQ)) == argQ
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define <bool> pol (AB == \A)
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set ffcepol pol
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semioptional
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endmatch
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code
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if (ffcemux) {
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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dffD = port(ffcemux, dffcepol ? \B : \A);
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}
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else
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dffcemux = nullptr;
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endcode
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// #######################
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subpattern out_dffe
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arg argD argQ clock
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arg unextend
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code
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dff = nullptr;
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endcode
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match ffcemux
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select ffcemux->type.in($mux)
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// ffcemux output must have two users: ffcemux and ff.D
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select nusers(port(ffcemux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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// keep-last-value net must have at least three users: ffcemux, ff, downstream sink(s)
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select nusers(port(ffcemux, AB)) >= 3
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slice offset GetSize(port(ffcemux, \Y))
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigBit> port(ffcemux, BA)[offset] === argD[0]
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set ffoffset offset
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define <bool> pol (BA == \B)
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set ffcepol pol
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semioptional
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endmatch
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code argD argQ
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dffcemux = ffcemux;
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if (ffcemux) {
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SigSpec BA = port(ffcemux, ffcepol ? \B : \A);
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if (ffoffset + GetSize(argD) > GetSize(BA))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (BA[ffoffset+i] != argD[i])
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reject;
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SigSpec Y = port(ffcemux, \Y);
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argQ = argD;
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argD.replace(BA, Y);
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argQ.replace(BA, port(ffcemux, ffcepol ? \A : \B));
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dffcemux = ffcemux;
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dffcepol = ffcepol;
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}
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endcode
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match ffrstmux
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select ffrstmux->type.in($mux)
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// ffrstmux output must have two users: ffrstmux and ff.D
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select nusers(port(ffrstmux, \Y)) == 2
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choice <IdString> BA {\B, \A}
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// DSP48E1 only supports reset to zero
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select port(ffrstmux, BA).is_fully_zero()
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slice offset GetSize(port(ffrstmux, \Y))
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define <IdString> AB (BA == \B ? \A : \B)
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index <SigBit> port(ffrstmux, AB)[offset] === argD[0]
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filter !ffcemux || ffoffset == offset
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set ffoffset offset
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define <bool> pol (AB == \A)
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set ffrstpol pol
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semioptional
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endmatch
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code argD argQ
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dffrstmux = ffrstmux;
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if (ffrstmux) {
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SigSpec AB = port(ffrstmux, ffcepol ? \A : \B);
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if (ffoffset + GetSize(argD) > GetSize(AB))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (AB[ffoffset+i] != argD[i])
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reject;
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SigSpec Y = port(ffrstmux, \Y);
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argD.replace(AB, Y);
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dffrstmux = ffrstmux;
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dffrstpol = ffrstpol;
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}
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endcode
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match ff
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select ff->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigSpec> port(ff, \D)[offset] === argD[0]
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filter (!ffcemux && !ffrstmux) || ffoffset == offset
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set ffoffset offset
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semioptional
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endmatch
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code argQ
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if (ff) {
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if (clock != SigBit()) {
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if (port(ff, \CLK) != clock)
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reject;
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}
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SigSpec D = port(ff, \D);
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if (ffoffset + GetSize(argD) > GetSize(D))
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reject;
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for (int i = 1; i < GetSize(argD); i++)
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if (D[ffoffset+i] != argD[i])
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reject;
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SigSpec Q = port(ff, \Q);
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if (ffcemux) {
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for (int i = 0; i < GetSize(argQ); i++)
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if (Q[ffoffset+i] != argQ[i])
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reject;
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}
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else {
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argQ = argD;
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argQ.replace(D, Q);
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}
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for (auto c : argQ.chunks()) {
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if (c.wire->get_bool_attribute(\keep))
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reject;
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Const init = c.wire->attributes.at(\init, State::Sx);
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if (!init.is_fully_undef() && !init.is_fully_zero())
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reject;
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}
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dff = ff;
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dffQ = argQ;
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dffclock = port(dff, \CLK);
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}
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// No enable/reset mux possible without flop
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else if (dffcemux || dffrstmux)
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reject;
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endcode
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