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yosys/frontends/ast
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Andrew Pullin deadaa9220 ast: Add support for array-to-array assignment 
This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
2026-01-23 11:06:08 -08:00
..
ast.cc Add CONST_FLAG_UNSIZED 2025-11-07 17:45:07 +13:00
ast.h Make AstNode::input_error use C++ stringf machinery 2025-09-12 06:01:32 +00:00
ast_binding.cc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
ast_binding.h Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
dpicall.cc Remove .c_str() calls from log()/log_error() 2025-09-11 20:59:37 +00:00
genrtlil.cc avoid merging formal properties 2025-12-17 20:25:24 +01:00
Makefile.inc Generate an RTLIL representation of bind constructs 2021-08-13 17:11:35 -06:00
simplify.cc ast: Add support for array-to-array assignment 2026-01-23 11:06:08 -08:00