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tests
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Bugfix in ice40_dsp
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2019-02-21 13:28:46 +01:00 |
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.gitignore
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Initialization support for all iCE40 bram modes
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2015-04-26 08:39:31 +02:00 |
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abc_hx.box
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Make SB_DFF whitebox
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2019-04-19 08:36:38 -07:00 |
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abc_hx.lut
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Fix rename
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2019-04-18 09:04:34 -07:00 |
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abc_lp.box
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Make SB_DFF whitebox
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2019-04-19 08:36:38 -07:00 |
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abc_lp.lut
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Rename to abc_*.{box,lut}
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2019-04-18 09:02:58 -07:00 |
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abc_u.box
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Make SB_DFF whitebox
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2019-04-19 08:36:38 -07:00 |
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abc_u.lut
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Rename to abc_*.{box,lut}
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2019-04-18 09:02:58 -07:00 |
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arith_map.v
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Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
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2019-04-17 11:10:20 -07:00 |
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brams.txt
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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brams_init.py
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Switched to Python 3
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2015-08-22 09:59:33 +02:00 |
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brams_map.v
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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2019-02-28 16:23:40 -08:00 |
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cells_map.v
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Map to SB_LUT4 from fastest input first
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2019-04-17 13:01:17 -07:00 |
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cells_sim.v
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Merge branch 'xaig' into xc7mux
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2019-05-31 13:03:03 -07:00 |
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ice40_braminit.cc
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Fix typo in ice40_braminit help msg
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2019-03-09 13:24:55 -08:00 |
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ice40_ffinit.cc
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Consistent use of 'override' for virtual methods in derived classes.
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2018-07-20 23:51:06 -07:00 |
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ice40_ffssr.cc
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ice40: Honor the "dont_touch" attribute in FFSSR pass
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2018-12-08 22:46:28 +01:00 |
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ice40_opt.cc
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Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues"
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2019-04-17 11:10:20 -07:00 |
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ice40_unlut.cc
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Extract ice40_unlut pass from ice40_opt.
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2018-12-05 16:30:24 +00:00 |
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latches_map.v
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Added synth_ice40 support for latches via logic loops
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2016-05-06 23:02:37 +02:00 |
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Makefile.inc
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Also update Makefile.inc
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2019-04-18 09:58:34 -07:00 |
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synth_ice40.cc
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Merge pull request #969 from YosysHQ/clifford/pmgenstuff
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2019-05-03 20:39:50 +02:00 |
