Marcelina Kościelnicka d3b6b7fe98 xilinx: Fix attributes_test.ys ... This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory.		2020-10-24 23:52:37 +02:00
..
.gitignore
abc9_dff.ys	abc9_ops: update messaging (credit to @Xiretza for spotting)	2020-05-30 08:57:48 -07:00
add_sub.ys	xilinx: Initial support for LUT4 devices.	2020-02-07 09:03:22 +01:00
adffs.ys
attributes_test.ys	xilinx: Fix attributes_test.ys	2020-10-24 23:52:37 +02:00
blockram.ys
bug1460.ys
bug1462.ys
bug1480.ys	Cleanup tests	2020-02-27 10:17:29 -08:00
bug1598.ys
bug1605.ys
counter.ys
dffs.ys	abc9_ops: -reintegrate to use derived_type for box_ports	2020-02-05 14:46:48 -08:00
dsp_abc9.ys	xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)	2020-09-23 09:15:24 -07:00
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys	synth_xilinx: Use opt_dff.	2020-07-30 22:26:09 +02:00
latches.ys	opt_expr: Remove -clkinv option, make it the default.	2020-07-31 00:08:15 +02:00
logic.ys
lutram.ys	xilinx: Add support for LUT RAM on LUT4-based devices.	2020-02-07 09:03:22 +01:00
macc.sh
macc.v	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc.ys	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
mux_lut4.ys	xilinx: Initial support for LUT4 devices.	2020-02-07 09:03:22 +01:00
nosrl.ys	xilinx: Fix srl regression.	2020-07-12 23:41:27 +02:00
opt_lut_ins.ys	Add opt_lut_ins pass. (#1673)	2020-02-03 14:57:17 +01:00
pmgen_xilinx_srl.ys	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	2020-07-24 03:19:21 +02:00
run-test.sh	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
shifter.ys
tribuf.sh	fix argument order for macOS compatibility	2020-03-18 15:11:49 +01:00
tribuf.ys
xilinx_dffopt.ys	xilinx: xilinx_dffopt to read cells_sim.v; fix test	2020-04-22 16:25:23 -07:00
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys	tests: read +/xilinx/cell_sim.v before xilinx_dsp test	2020-04-22 17:50:30 -07:00
xilinx_srl.v	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
xilinx_srl.ys