mirror of
https://github.com/YosysHQ/yosys
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44 lines
1.1 KiB
Python
44 lines
1.1 KiB
Python
#!/usr/bin/env python3
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import sys
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sys.path.append("..")
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import shutil
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import os
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from pathlib import Path
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# ----------------------
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# Check if iverilog is installed
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# ----------------------
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if shutil.which("iverilog") is None:
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print("Error: Icarus Verilog 'iverilog' not found.", file=sys.stderr)
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sys.exit(1)
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src_dir = Path("../simple")
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# ----------------------
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# Copy all files from ../simple to current directory
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# ----------------------
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for file in src_dir.glob("*.v"):
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shutil.copy(file, os.path.join(".", file.name))
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for file in src_dir.glob("*.sv"):
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shutil.copy(file, os.path.join(".", file.name))
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# bug 2675
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bug_file = os.path.join(".", "specify.v")
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if os.path.exists(bug_file):
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os.remove(bug_file)
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import gen_tests_makefile
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gen_tests_makefile.generate_autotest("*.*v", "-f \"verilog -noblackbox -specify\" -n 300 -p '\
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read_verilog -icells -lib +/abc9_model.v; \
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hierarchy; \
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synth -run coarse; \
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opt -full; \
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techmap; \
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abc9 -lut 4; \
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clean; \
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check -assert * abc9_test037 %d; \
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select -assert-none t:?_NOT_ t:?_AND_ %%; \
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setattr -mod -unset blackbox -unset whitebox =*'")
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