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30 lines
795 B
Text
30 lines
795 B
Text
read_verilog <<EOT
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module foo(
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output o,
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input [0:0] i1,
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input i2
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);
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wire [0:0] w1 = i1 ^ i2;
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wire w2 = ~i1;
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assign o = w1 ^ w2;
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endmodule
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EOT
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hierarchy
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proc
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select -assert-count 1 w:i1
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select -assert-count 1 w:i1 a:single_bit_vector %i
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select -assert-count 1 w:i2
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select -assert-count 0 w:i2 a:single_bit_vector %i
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select -assert-count 1 w:w1
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select -assert-count 1 w:w1 a:single_bit_vector %i
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select -assert-count 1 w:w2
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select -assert-count 0 w:w2 a:single_bit_vector %i
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write_verilog verilog_sbvector.out
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!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
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!grep -qF 'input [0:0] i1;' verilog_sbvector.out
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!grep -qF 'wire i2;' verilog_sbvector.out
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!grep -qF 'input i2;' verilog_sbvector.out
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!grep -qF 'wire [0:0] w1;' verilog_sbvector.out
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!grep -qF 'wire w2;' verilog_sbvector.out
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