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				https://github.com/YosysHQ/yosys
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	- track depth so we know whether to consider higher-level elsifs - error on unmatched endif/elsif/else
		
			
				
	
	
		
			30 lines
		
	
	
	
		
			393 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			30 lines
		
	
	
	
		
			393 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
`ifdef GUARD_5
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module top;
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	wire x;
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endmodule
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`elsif GUARD_4
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`define GUARD_5
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`include "include_self.v"
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`elsif GUARD_3
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`define GUARD_4
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`include "include_self.v"
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`elsif GUARD_2
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`define GUARD_3
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`include "include_self.v"
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`elsif GUARD_1
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`define GUARD_2
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`include "include_self.v"
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`elsif GUARD_0
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`define GUARD_1
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`include "include_self.v"
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`else
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`define GUARD_0
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`include "include_self.v"
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`endif
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