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https://github.com/YosysHQ/yosys
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5e641acc90
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
135 lines
2.2 KiB
Verilog
135 lines
2.2 KiB
Verilog
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// test_simulation_always_15_test.v
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module f1_test(input [1:0] in, output reg [1:0] out);
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always @(in)
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out = in;
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endmodule
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// test_simulation_always_17_test.v
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module f2_test(a, b, c, d, z);
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input a, b, c, d;
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output z;
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reg z, temp1, temp2;
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always @(a or b or c or d)
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begin
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temp1 = a ^ b;
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temp2 = c ^ d;
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z = temp1 ^ temp2;
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end
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endmodule
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// test_simulation_always_18_test.v
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module f3_test (in1, in2, out);
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input in1, in2;
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output reg out;
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always @ ( in1 or in2)
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if(in1 > in2)
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out = in1;
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else
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out = in2;
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endmodule
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// test_simulation_always_19_test.v
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module f4_test(ctrl, in1, in2, out);
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input ctrl;
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input in1, in2;
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output reg out;
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always @ (ctrl or in1 or in2)
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if(ctrl)
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out = in1 & in2;
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else
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out = in1 | in2;
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endmodule
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// test_simulation_always_1_test.v
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module f5_test(input in, output reg out);
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always @(in)
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out = in;
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endmodule
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// test_simulation_always_20_test.v
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module f6_NonBlockingEx(clk, merge, er, xmit, fddi, claim);
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input clk, merge, er, xmit, fddi;
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output reg claim;
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reg fcr;
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always @(posedge clk)
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begin
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fcr <= er | xmit;
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if(merge)
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claim <= fcr & fddi;
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else
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claim <= fddi;
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end
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endmodule
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// test_simulation_always_21_test.v
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module f7_FlipFlop(clk, cs, ns);
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input clk;
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input [7:0] cs;
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output [7:0] ns;
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integer is;
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always @(posedge clk)
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is <= cs;
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assign ns = is;
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endmodule
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// test_simulation_always_22_test.v
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module f8_inc(clock, counter);
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input clock;
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output reg [7:0] counter;
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always @(posedge clock)
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counter <= counter + 1;
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endmodule
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// test_simulation_always_23_test.v
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module f9_MyCounter (clock, preset, updown, presetdata, counter);
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input clock, preset, updown;
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input [1: 0] presetdata;
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output reg [1:0] counter;
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always @(posedge clock)
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if(preset)
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counter <= presetdata;
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else
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if(updown)
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counter <= counter + 1;
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else
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counter <= counter - 1;
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endmodule
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// test_simulation_always_27_test.v
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module f10_FlipFlop(clock, cs, ns);
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input clock;
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input cs;
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output reg ns;
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reg temp;
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always @(posedge clock)
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begin
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temp <= cs;
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ns <= temp;
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end
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endmodule
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// test_simulation_always_29_test.v
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module f11_test(input in, output reg [1:0] out);
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always @(in)
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begin
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out = in;
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out = out + in;
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end
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endmodule
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