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32 lines
661 B
Verilog
32 lines
661 B
Verilog
module $__ANLOGIC_DRAM16X4_ (...);
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parameter INIT = 64'b0;
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input PORT_W_CLK;
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input [3:0] PORT_W_ADDR;
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input [3:0] PORT_W_WR_DATA;
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input PORT_W_WR_EN;
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input [3:0] PORT_R_ADDR;
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output [3:0] PORT_R_RD_DATA;
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function [15:0] init_slice;
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input integer idx;
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integer i;
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for (i = 0; i < 16; i = i + 1)
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init_slice[i] = INIT[i * 4 + idx];
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endfunction
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EG_LOGIC_DRAM16X4 #(
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.INIT_D0(init_slice(0)),
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.INIT_D1(init_slice(1)),
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.INIT_D2(init_slice(2)),
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.INIT_D3(init_slice(3))
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) _TECHMAP_REPLACE_ (
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.di(PORT_W_WR_DATA),
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.waddr(PORT_W_ADDR),
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.wclk(PORT_W_CLK),
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.we(PORT_W_WR_EN),
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.raddr(PORT_R_ADDR),
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.do(PORT_R_RD_DATA)
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);
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endmodule
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