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Code Activity
yosys/techlibs/xilinx
History
Eddie Hung 8469d9fe9f Missing newline
2019-04-26 14:51:37 -07:00
..
tests
.gitignore
abc.box Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
abc.lut Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
arith_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
brams.txt Added read-enable to memory model 2015-09-25 12:23:11 +02:00
brams_bb.v
brams_init.py Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
brams_map.v Revert BRAM WRITE_MODE changes. 2019-03-04 09:22:22 -08:00
cells_map.v Cleanup superseded 2019-04-25 19:43:41 -07:00
cells_sim.v Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
cells_xtra.sh Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
cells_xtra.v Merge remote-tracking branch 'origin' into xc7srl 2019-04-20 10:41:43 -07:00
drams.txt
drams_map.v
ff_map.v Tidy up, fix for -nosrl 2019-04-21 15:33:03 -07:00
lut_map.v Changes required for VPR place and route synth_xilinx. 2019-03-01 12:02:27 -08:00
Makefile.inc Cleanup, call pmux2shiftx even without -nosrl 2019-04-22 12:14:37 -07:00
synth_xilinx.cc Missing newline 2019-04-26 14:51:37 -07:00