Miodrag Milanovic ff8e999a71 Split module ports, 20 per line		2021-10-09 13:40:55 +02:00
..
aiger
blif
btor	Hook up $aldff support in various passes.	2021-10-02 21:01:21 +02:00
cxxrtl	Hook up $aldff support in various passes.	2021-10-02 21:01:21 +02:00
edif
firrtl
intersynth
json
protobuf
rtlil	Add optimization to rtlil back-end for all-x parameter values	2021-09-27 16:02:20 +02:00
simplec
smt2	Hook up $aldff support in various passes.	2021-10-02 21:01:21 +02:00
smv	Hook up $aldff support in various passes.	2021-10-02 21:01:21 +02:00
spice
table
verilog	Split module ports, 20 per line	2021-10-09 13:40:55 +02:00