yosys/docs/source/code_examples/synth_flow/proc_01.ys at dc746080f501986782730fc0f7ae3ba2d08d1068 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 18:15:34 +00:00

Krystine Sherwin dbc38d72cf

docs: moving code examples

Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.

2023-11-14 12:55:39 +13:00

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Raw Blame History

	`read_verilog proc_01.v`
	`hierarchy -check -top test`
	`proc;;`