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yosys/passes
2026-03-18 16:23:41 -07:00
..
cmds Merge from main 2026-02-13 04:14:08 -08:00
equiv
fsm
hierarchy
memory Fix cell naming issues 2026-02-13 01:05:51 -08:00
opt Improve wreduce runtime 2026-02-19 01:03:26 -08:00
pmgen
proc
sat Added new passes/sat/struct_partition.cc pass to propagate the ports out 2026-03-18 11:53:47 -07:00
silimate Merge branch 'main' into sat_clkgate 2026-03-03 20:57:42 -08:00
techmap Added support for printing the signal map 2026-03-18 16:23:41 -07:00
tests