Emil J. Tywoniak dc204dc909 Revert "verilog: add support for SystemVerilog string literals." ... This reverts commit 5feb1a1752.		2025-07-10 21:14:38 +02:00
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source	Revert "verilog: add support for SystemVerilog string literals."	2025-07-10 21:14:38 +02:00
tests	docs: Fix macro_commands	2024-05-10 09:51:37 +12:00
util	Docs: Render cell titles	2024-10-15 07:35:42 +13:00
.gitignore	Docs: Rename source/temp to source/generated	2024-04-15 10:13:22 +12:00
Makefile	Makefile: Combine gen_images and gen_examples	2024-10-17 07:12:34 +13:00