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87 lines
1.4 KiB
Verilog
87 lines
1.4 KiB
Verilog
(* techmap_celltype = "$_NOT_" *)
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module _90_lut_not (A, Y);
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input A;
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output Y;
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wire [`LUT_WIDTH-1:0] AA;
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assign AA = {A};
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\$lut #(
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.WIDTH(`LUT_WIDTH),
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.LUT(4'b01)
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) lut (
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.A(AA),
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.Y(Y)
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);
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endmodule
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(* techmap_celltype = "$_OR_" *)
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module _90_lut_or (A, B, Y);
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input A, B;
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output Y;
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wire [`LUT_WIDTH-1:0] AA;
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assign AA = {B, A};
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\$lut #(
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.WIDTH(`LUT_WIDTH),
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.LUT(4'b1110)
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) lut (
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.A(AA),
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.Y(Y)
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);
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endmodule
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(* techmap_celltype = "$_AND_" *)
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module _90_lut_and (A, B, Y);
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input A, B;
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output Y;
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wire [`LUT_WIDTH-1:0] AA;
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assign AA = {B, A};
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\$lut #(
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.WIDTH(`LUT_WIDTH),
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.LUT(4'b1000)
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) lut (
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.A(AA),
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.Y(Y)
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);
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endmodule
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(* techmap_celltype = "$_XOR_" *)
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module _90_lut_xor (A, B, Y);
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input A, B;
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output Y;
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wire [`LUT_WIDTH-1:0] AA;
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assign AA = {B, A};
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\$lut #(
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.WIDTH(`LUT_WIDTH),
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.LUT(4'b0110)
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) lut (
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.A(AA),
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.Y(Y)
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);
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endmodule
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(* techmap_celltype = "$_MUX_" *)
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module _90_lut_mux (A, B, S, Y);
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input A, B, S;
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output Y;
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wire [`LUT_WIDTH-1:0] AA;
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assign AA = {S, B, A};
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\$lut #(
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.WIDTH(`LUT_WIDTH),
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// A 1010 1010
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// B 1100 1100
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// S 1111 0000
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.LUT(8'b 1100_1010)
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) lut (
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.A(AA),
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.Y(Y)
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);
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endmodule
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