Marcelina Kościelnicka dc07ae9677 techmap: Add _TECHMAP_CELLNAME_ special parameter. ... This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.		2020-07-21 15:00:54 +02:00
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aiger	tests: aiger test for wire->start_offset != 0	2020-05-02 10:00:32 -07:00
arch	Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogic	2020-07-16 18:07:58 +02:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bram	Added support for (single-clock) transparent memories to bram tests	2016-11-01 10:03:13 +01:00
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm	tests: fsm to use a randomly-generated seed	2020-04-24 14:31:33 -07:00
hana	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
liberty	dfflibmap: Refactor to use dfflegalize internally.	2020-07-09 18:51:03 +02:00
lut	Forgot to commit	2019-07-16 12:44:26 -07:00
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories	memory_dff: Fix checking of feedback mux input when more than one mux	2019-07-02 13:35:50 +01:00
opt	opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.	2020-07-05 06:31:58 +02:00
opt_share	Support various binary operators in opt_share	2019-08-04 19:06:38 +02:00
proc	proc_clean: fix order of switch insertion.	2019-08-19 16:44:23 +00:00
realmath	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	Merge pull request #1638 from YosysHQ/eddie/fix1631	2020-02-05 19:31:18 +01:00
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
simple	Expand tests/simple/constmuldivmod.v	2020-05-28 22:59:04 +02:00
simple_abc9	abc9: test to use box file instead of auto	2020-05-14 10:33:56 -07:00
smv	Progress in SMV back-end	2015-06-19 14:08:46 +02:00
sva	Fix "verific -extnets" for more complex situations	2019-03-26 14:17:46 +01:00
svinterfaces	Fix typo in tests/svinterfaces/runone.sh	2019-05-03 14:40:51 +02:00
svtypes	static cast: add tests	2020-06-19 17:40:38 -07:00
techmap	techmap: Add _TECHMAP_CELLNAME_ special parameter.	2020-07-21 15:00:54 +02:00
tools	autotest.sh to define _AUTOTB when test_autotb	2019-06-28 14:56:22 -07:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	Revert "Revert PRs #2203 and #2244."	2020-07-10 09:59:48 +02:00
verilog	Merge pull request #2080 from YosysHQ/eddie/fix_test_warnings	2020-06-03 08:37:07 -07:00
vloghtb	bugfix in blif front-end	2015-05-18 11:15:49 +02:00